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sandybridge: enable ROM caching 

If ROM caching is selected the sandybridge chipset code will
will enable ROM caching after all other CPU threads are brought
up.

Change-Id: I3a57ba8753678146527ebf9547f5fbbd4f441f43
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3017
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Aaron Durbin 2013-04-03 09:56:57 -05:00 committed by Stefan Reinauer
parent 23f50166c6
commit c6f27226a8
1 changed files with 3 additions and 0 deletions
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3
src/northbridge/intel/sandybridge/northbridge.c
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@ -25,6 +25,7 @@
#include <delay.h>
#include <cpu/intel/model_206ax/model_206ax.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
@ -486,6 +487,8 @@ static const struct pci_driver mc_driver_1 __pci_driver = {
static void cpu_bus_init(device_t dev)
{
initialize_cpus(dev->link_list);
/* Enable ROM caching if option was selected. */
x86_mtrr_enable_rom_caching();
}
static void cpu_bus_noop(device_t dev)