soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC

Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC

Change-Id: I6a44d55d1588d2620bd1179ea7dc327922f49fd7
Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com>
Reviewed-on: https://review.coreboot.org/18028
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

src/soc/intel/skylake/bootblock/report_platform.c

@@ -32,8 +32,12 @@ static struct {
 } cpu_table[] = {
 	{ CPUID_SKYLAKE_C0,	"Skylake C0" },
 	{ CPUID_SKYLAKE_D0,	"Skylake D0" },
+	{ CPUID_SKYLAKE_HQ0,    "Skylake H Q0" },
+	{ CPUID_SKYLAKE_HR0,    "Skylake H R0" },
 	{ CPUID_KABYLAKE_G0,	"Kabylake G0" },
 	{ CPUID_KABYLAKE_H0,	"Kabylake H0" },
+	{ CPUID_KABYLAKE_HA0,	"Kabylake H A0" },
+	{ CPUID_KABYLAKE_HB0,	"Kabylake H B0" },
 };
 
 static struct {
@@ -43,8 +47,11 @@ static struct {
 	{ MCH_SKYLAKE_ID_U,	"Skylake-U" },
 	{ MCH_SKYLAKE_ID_Y,	"Skylake-Y" },
 	{ MCH_SKYLAKE_ID_ULX,	"Skylake-ULX" },
+	{ MCH_SKYLAKE_ID_H,	"Skylake-H" },
+	{ MCH_SKYLAKE_ID_H_EM,  "Skylake-H Embedded" },
 	{ MCH_KABYLAKE_ID_U,	"Kabylake-U" },
 	{ MCH_KABYLAKE_ID_Y,	"Kabylake-Y" },
+	{ MCH_KABYLAKE_ID_H,	"Kabylake-H" },
 };
 
 static struct {
@@ -55,6 +62,9 @@ static struct {
 	{ PCH_SPT_LP_U_BASE,		"Skylake-U Base" },
 	{ PCH_SPT_LP_U_PREMIUM,		"Skylake-U Premium" },
 	{ PCH_SPT_LP_Y_PREMIUM,		"Skylake-Y Premium" },
+	{ PCH_SPT_H_PREMIUM,		"Skylake-H Premium" },
+	{ PCH_SPT_H_C236,		"Skylake-H C236" },
+	{ PCH_SPT_H_QM170,		"Skylake-H QM170" },
 	{ PCH_KBL_LP_U_PREMIUM,		"Kabylake-U Premium" },
 	{ PCH_KBL_LP_Y_PREMIUM,		"Kabylake-Y Premium" },
 	{ PCH_KBL_LP_Y_PREMIUM_HDCP22,	"Kabylake-Y iHDCP 2.2 Premium" },
@@ -67,9 +77,12 @@ static struct {
 	{ IGD_SKYLAKE_GT1_SULTM, "Skylake ULT GT1"},
 	{ IGD_SKYLAKE_GT2_SULXM, "Skylake ULX GT2" },
 	{ IGD_SKYLAKE_GT2_SULTM, "Skylake ULT GT2" },
+	{ IGD_SKYLAKE_GT2_SHALM, "Skylake HALO GT2" },
+	{ IGD_SKYLAKE_GT4_SHALM, "Skylake HALO GT4" },
 	{ IGD_KABYLAKE_GT1_SULTM, "Kabylake ULT GT1"},
 	{ IGD_KABYLAKE_GT2_SULXM, "Kabylake ULX GT2" },
 	{ IGD_KABYLAKE_GT2_SULTM, "Kabylake ULT GT2" },
+	{ IGD_KABYLAKE_GT2_SHALM, "Kabylake HALO GT2" },
 };
 
 static void report_cpu_info(void)

src/soc/intel/skylake/cpu.c

@@ -385,8 +385,12 @@ static struct device_operations cpu_dev_ops = {
 static struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_C0 },
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_D0 },
+	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0 },
+	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_HR0 },
 	{ X86_VENDOR_INTEL, CPUID_KABYLAKE_G0 },
 	{ X86_VENDOR_INTEL, CPUID_KABYLAKE_H0 },
+	{ X86_VENDOR_INTEL, CPUID_KABYLAKE_HA0 },
+	{ X86_VENDOR_INTEL, CPUID_KABYLAKE_HB0 },
 	{ 0, 0 },
 };
 

src/soc/intel/skylake/igd.c

@@ -190,9 +190,12 @@ static const unsigned short pci_device_ids[] = {
 	IGD_SKYLAKE_GT1_SULTM,
 	IGD_SKYLAKE_GT2_SULXM,
 	IGD_SKYLAKE_GT2_SULTM,
+	IGD_SKYLAKE_GT2_SHALM,
+	IGD_SKYLAKE_GT4_SHALM,
 	IGD_KABYLAKE_GT1_SULTM,
 	IGD_KABYLAKE_GT2_SULXM,
 	IGD_KABYLAKE_GT2_SULTM,
+	IGD_KABYLAKE_GT2_SHALM,
 	0,
 };
 

src/soc/intel/skylake/include/soc/cpu.h

@@ -26,8 +26,12 @@
 /* Supported CPUIDs */
 #define CPUID_SKYLAKE_C0	0x406e2
 #define CPUID_SKYLAKE_D0	0x406e3
+#define CPUID_SKYLAKE_HQ0	0x506e1
+#define CPUID_SKYLAKE_HR0	0x506e3
 #define CPUID_KABYLAKE_G0	0x406e8
 #define CPUID_KABYLAKE_H0	0x806e9
+#define CPUID_KABYLAKE_HA0	0x506e8
+#define CPUID_KABYLAKE_HB0	0x906e9
 
 /* CPU bus clock is fixed at 100MHz */
 #define CPU_BCLK		100

src/soc/intel/skylake/include/soc/pch.h

@@ -26,6 +26,9 @@
 #define PCH_SPT_LP_U_BASE		0x9d43
 #define PCH_SPT_LP_U_PREMIUM		0x9d48
 #define PCH_SPT_LP_Y_PREMIUM		0x9d46
+#define PCH_SPT_H_C236			0xa150
+#define PCH_SPT_H_PREMIUM		0xa14e
+#define PCH_SPT_H_QM170			0xa14d
 #define PCH_KBL_LP_Y_PREMIUM_HDCP22	0x9d4b
 #define PCH_KBL_LP_U_PREMIUM		0x9d58
 #define PCH_KBL_LP_Y_PREMIUM		0x9d56

src/soc/intel/skylake/include/soc/systemagent.h

@@ -25,15 +25,21 @@
 #define IGD_SKYLAKE_GT1_SULTM	0x1906
 #define IGD_SKYLAKE_GT2_SULXM	0x191E
 #define IGD_SKYLAKE_GT2_SULTM	0x1916
+#define IGD_SKYLAKE_GT2_SHALM	0x191B
+#define IGD_SKYLAKE_GT4_SHALM	0x193D
 #define IGD_KABYLAKE_GT1_SULTM	0x5906
 #define IGD_KABYLAKE_GT2_SULXM	0x591E
 #define IGD_KABYLAKE_GT2_SULTM	0x5916
+#define IGD_KABYLAKE_GT2_SHALM	0x591B
 
 #define MCH_SKYLAKE_ID_U	0x1904
 #define MCH_SKYLAKE_ID_Y	0x190c
 #define MCH_SKYLAKE_ID_ULX	0x1924
+#define MCH_SKYLAKE_ID_H	0x1910
+#define MCH_SKYLAKE_ID_H_EM	0x1918
 #define MCH_KABYLAKE_ID_U	0x5904
 #define MCH_KABYLAKE_ID_Y	0x590c
+#define MCH_KABYLAKE_ID_H	0x5910
 
 /* Device 0:0.0 PCI configuration space */
 

src/soc/intel/skylake/lpc.c

@@ -317,6 +317,9 @@ static const unsigned short pci_device_ids[] = {
 	PCH_SPT_LP_U_BASE,
 	PCH_SPT_LP_U_PREMIUM,
 	PCH_SPT_LP_Y_PREMIUM,
+	PCH_SPT_H_QM170,
+	PCH_SPT_H_PREMIUM,
+	PCH_SPT_H_C236,
 	PCH_KBL_LP_U_PREMIUM,
 	PCH_KBL_LP_Y_PREMIUM,
 	PCH_KBL_LP_Y_PREMIUM_HDCP22,

src/soc/intel/skylake/pcie.c

@@ -96,6 +96,12 @@ static const unsigned short pcie_device_ids[] = {
 	/* Sunrisepoint-LP */
 	0x9d10, 0x9d11, 0x9d12, 0x9d13, 0x9d14, 0x9d15, 0x9d16, 0x9d17,
 	0x9d18, 0x9d19, 0x9d1a, 0x9d1b,
+	/* Sunrisepoint-H */
+	0xa290, 0xa291, 0xa292, 0xa293, 0xa294, 0xa295, 0xa296, 0xa297,
+	0xa298, 0xa299, 0xa29a, 0xa29b, 0xa29c, 0xa29d, 0xa29e, 0xa20f,
+	0xa110, 0xa111, 0xa112, 0xa113, 0xa114, 0xa115, 0xa116, 0xa117,
+	0xa118, 0xa119, 0xa11a, 0xa11b, 0xa11c, 0xa11d, 0xa11e, 0xa11f,
+	0xa167, 0xa168, 0xa169, 0xa16a,
 	0
 };
 

src/soc/intel/skylake/pmc.c

@@ -244,6 +244,7 @@ static struct device_operations device_ops = {
 
 static const unsigned short pci_device_ids[] = {
 	0x9d21,
+	0xa121,
 	0
 };
 

src/soc/intel/skylake/smbus.c

@@ -99,6 +99,7 @@ static struct device_operations smbus_ops = {
 
 static const unsigned short pci_device_ids[] = {
 	0x9d23, /* SunRisePoint LP */
+	0xa123, /* SunRisePoint H */
 	0
 };
 

src/soc/intel/skylake/systemagent.c

@@ -414,8 +414,11 @@ static const unsigned short systemagent_ids[] = {
 	MCH_SKYLAKE_ID_U,
 	MCH_SKYLAKE_ID_Y,
 	MCH_SKYLAKE_ID_ULX,
+	MCH_SKYLAKE_ID_H,
+	MCH_SKYLAKE_ID_H_EM,
 	MCH_KABYLAKE_ID_U,
 	MCH_KABYLAKE_ID_Y,
+	MCH_KABYLAKE_ID_H,
 	0
 };
 

src/soc/intel/skylake/uart.c

@@ -53,6 +53,9 @@ static const unsigned short pci_device_ids[] = {
 	0x9d27, /* UART0 */
 	0x9d28, /* UART1 */
 	0x9d66, /* UART2 */
+	0xa127, /* KBL-H UART0 */
+	0xa128, /* KBL-H UART1 */
+	0xa166, /* KBL-H UART2 */
 	0
 };
 

src/soc/intel/skylake/xhci.c

@@ -33,6 +33,7 @@ static struct device_operations usb_xhci_ops = {
 
 static const unsigned short pci_device_ids[] = {
 	0x9d2f, /* SunRisePoint LP */
+	0xa12f, /* KBL-H*/
 	0
 };