c76e9982b2
Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC Change-Id: I6a44d55d1588d2620bd1179ea7dc327922f49fd7 Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com> Reviewed-on: https://review.coreboot.org/18028 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
206 lines
5.7 KiB
C
206 lines
5.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <bootmode.h>
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#include <chip.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <drivers/intel/gma/i915_reg.h>
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#include <fsp/util.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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#include <soc/pm.h>
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#include <soc/ramstage.h>
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#include <soc/systemagent.h>
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#include <stdlib.h>
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#include <string.h>
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#include <vboot/vbnv.h>
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uintptr_t fsp_soc_get_igd_bar(void)
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{
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return find_resource(SA_DEV_IGD, PCI_BASE_ADDRESS_2)->base;
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}
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u32 map_oprom_vendev(u32 vendev)
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{
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return SA_IGD_OPROM_VENDEV;
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}
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static struct resource *gtt_res = NULL;
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static unsigned long gtt_read(unsigned long reg)
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{
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u32 val;
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val = read32((void *)(unsigned int)(gtt_res->base + reg));
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return val;
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}
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static void gtt_write(unsigned long reg, unsigned long data)
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{
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write32((void *)(unsigned int)(gtt_res->base + reg), data);
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}
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static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
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{
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u32 val = gtt_read(reg);
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val &= andmask;
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val |= ormask;
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gtt_write(reg, val);
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}
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static void igd_init(struct device *dev)
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{
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u32 ddi_buf_ctl;
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gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (!gtt_res || !gtt_res->base)
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return;
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/*
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* Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
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* This will allow the kernel to use 4-lane eDP links properly
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* if the VBIOS or GOP driver does not execute.
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*/
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ddi_buf_ctl = gtt_read(DDI_BUF_CTL_A);
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if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
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ddi_buf_ctl |= DDI_A_4_LANES;
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gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
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}
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if (IS_ENABLED(CONFIG_ADD_VBT_DATA_FILE))
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return;
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/* IGD needs to be Bus Master */
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u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* Wait for any configured pre-graphics delay */
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if (!acpi_is_wakeup_s3()) {
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#if IS_ENABLED(CONFIG_CHROMEOS)
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if (display_init_required() || vboot_wants_oprom())
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mdelay(CONFIG_PRE_GRAPHICS_DELAY);
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#else
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mdelay(CONFIG_PRE_GRAPHICS_DELAY);
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#endif
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}
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/* Initialize PCI device, load/execute BIOS Option ROM */
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pci_dev_init(dev);
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#if IS_ENABLED(CONFIG_CHROMEOS)
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if (!gfx_get_init_done() && !acpi_is_wakeup_s3()) {
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/*
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* Enable DDI-A if the Option ROM did not execute:
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*
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* bit 0: Display detected (RO)
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* bit 4: DDI A supports 4 lanes and DDI E is not used
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* bit 7: DDI buffer is idle
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*/
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gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES |
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DDI_INIT_DISPLAY_DETECTED);
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}
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#endif
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}
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/* Initialize IGD OpRegion, called from ACPI code */
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static int update_igd_opregion(igd_opregion_t *opregion)
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{
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u16 reg16;
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/* Initialize Mailbox 3 */
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opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
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opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
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opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
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opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
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opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
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opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
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opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
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opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
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opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
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opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
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opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
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opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
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opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
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opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
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opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
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/* TODO This may need to happen in S3 resume */
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pci_write_config32(SA_DEV_IGD, ASLS, (u32)opregion);
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reg16 = pci_read_config16(SA_DEV_IGD, SWSCI);
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reg16 &= ~GSSCIE;
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reg16 |= SMISCISEL;
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pci_write_config16(SA_DEV_IGD, SWSCI, reg16);
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return 0;
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}
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static unsigned long write_acpi_igd_opregion(device_t device,
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unsigned long current, struct acpi_rsdp *rsdp)
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{
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igd_opregion_t *opregion;
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/* If GOP is not used, exit here */
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if (!IS_ENABLED(CONFIG_ADD_VBT_DATA_FILE))
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return current;
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/* If IGD is disabled, exit here */
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if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF)
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return current;
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printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
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opregion = (igd_opregion_t *)current;
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init_igd_opregion(opregion);
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update_igd_opregion(opregion);
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current += sizeof(igd_opregion_t);
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current = acpi_align_current(current);
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printk(BIOS_DEBUG, "current = %lx\n", current);
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return current;
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}
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static struct device_operations igd_ops = {
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.read_resources = &pci_dev_read_resources,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.init = &igd_init,
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.ops_pci = &soc_pci_ops,
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.write_acpi_tables = write_acpi_igd_opregion,
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};
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static const unsigned short pci_device_ids[] = {
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IGD_SKYLAKE_GT1_SULTM,
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IGD_SKYLAKE_GT2_SULXM,
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IGD_SKYLAKE_GT2_SULTM,
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IGD_SKYLAKE_GT2_SHALM,
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IGD_SKYLAKE_GT4_SHALM,
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IGD_KABYLAKE_GT1_SULTM,
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IGD_KABYLAKE_GT2_SULXM,
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IGD_KABYLAKE_GT2_SULTM,
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IGD_KABYLAKE_GT2_SHALM,
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0,
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};
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static const struct pci_driver igd_driver __pci_driver = {
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.ops = &igd_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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