northbridge/via/vx800/examples: Remove rotting source
This is just bit-rotting and its likely this will continue to rot by the time someone notices it exits it will be too late (i.e., today). Change-Id: I40ef2cd8e3d563079b086f51dabab0960a0a13b3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8087 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Edward O'Callaghan
parent
c3fde7ef36
commit
c800199007
File diff suppressed because it is too large
Load Diff
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@ -1,242 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 One Laptop per Child, Association, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "northbridge/via/vx800/driving_clk_phase_data.h"
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// DQS Driving
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//Reg0xE0, 0xE1
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// According to #Bank to set DRAM DQS Driving
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// #Bank 1 2 3 4 5 6 7 8
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static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE};
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static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE};
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// DQ Driving
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//Reg0xE2, 0xE3
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// For DDR2: According to bank to set DRAM DQ Driving
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static const u8 DDR2_DQA_Driving_Table[4] = { 0xAC, 0xAC, 0xAC, 0xAC };
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static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA };
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// CS Driving
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//Reg0xE4, 0xE5
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// According to #Bank to set DRAM CS Driving
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// DDR1 #Bank 1 2 3 4 5 6 7 8
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static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 };
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static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44};
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static const u8 DDR2_CSA_Driving_Table_x16[4]= { 0x44, 0x44, 0x44, 0x44};
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static const u8 DDR2_CSB_Driving_Table_x16[2]= { 0x44, 0x44};
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// MAA Driving
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//Reg0xE8, Reg0xE9
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static const u8 DDR2_MAA_Driving_Table[MA_Table][5] =
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{
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//Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8
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{ 6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06
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{ 18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18
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{255, 0xDB, 0xDB, 0xDB, 0xDB} // total MAA chips = 18 ~
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};
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static const u8 DDR2_MAB_Driving_Table[MA_Table][2] =
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{
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// Chip number, Value ;(SRAS, SCAS, SWE)RxE9
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{ 6, 0x86 }, // total MAB chips = 00 ~ 06
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{ 18, 0x86 }, // total MAB chips = 06 ~ 18
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{255, 0xDB } // total MAB chips = 18 ~
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};
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// DCLK Driving
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//Reg0xE6, 0xE7
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// For DDR2: According to #Freq to set DRAM DCLK Driving
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// freq 400M, 533M, 667M, 800M
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static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
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static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
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/*
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Duty cycle
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Duty cycle Control for DQ/DQS/DDRCKG in ChA & ChB
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D0F3RxEC/D0F3RxED/D0F3RxEE/D0F3RxEF
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According to DRAM frequency to control Duty Cycle
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*/
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static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0xEC, 0x00, 0x30, 0x30, 0x30, 0x30 }, // 1Rank
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{0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00 },
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{0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30}
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};
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static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0xED, 0x00, 0x88, 0x88, 0x84, 0x88 }, // 1Rank
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{0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00 },
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{0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00 }
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};
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/*
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DRAM Clock Phase Control for FeedBack Mode
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Modify NB Reg: Rx90[7]/Rx91/Rx92/Rx93/Rx94
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Processing:
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1.Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode
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2.Program clock phase value with ChA/B DCLK enable, VIA_NB3DRAM_REG91[7:3]=00b
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3.Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO
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ChA DCLKO can not be disable, so always program VIA_NB3DRAM_REG91[3]=0b
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*/
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static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x91, 0xF8, 0x02, 0x01, 0x00, 0x07 }, // 1Rank
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{0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 },
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{0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 }
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};
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static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x91, 0x0F, 0x20, 0x10, 0x00, 0x70 }, // 1Rank
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{0x92, 0x0F, 0x40, 0x30, 0x30, 0x20 },
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{0x93, 0x0F, 0x60, 0x50, 0x40, 0x30 }
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};
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/*static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 }, // 1Rank
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{0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 },
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{0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 }
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};*/
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static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank
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{0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 },
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{0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 }
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};
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/*
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DRAM Write Data phase control
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Modify NB Reg: Rx74/Rx75/Rx76
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*/
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/*static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 }, // 1Rank
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{0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 },
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{0x76, 0x00, 0x10, 0x80, 0x00, 0x07 }
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};*/
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static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x74, 0xF8, 0x01, 0x00, 0x00, 0x07 }, // 1Rank
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{0x75, 0xF8, 0x01, 0x00, 0x00, 0x07 },
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{0x76, 0x10, 0x80, 0x87, 0x07, 0x06 },
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{0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03 }
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};
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/*static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank
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{0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 },
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{0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 }
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};
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*/
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/*
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DQ/DQS Output Delay Control
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Modify NB D0F3: RxF0/RxF1/RxF2/RxF3
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*/
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static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] =
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{
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// RxF0 RxF1 RxF2 RxF3
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{ 0x00, 0x00, 0x00, 0x00 },// DDR400
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{ 0x00, 0x00, 0x00, 0x00 },// DDR533
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{ 0x00, 0x00, 0x00, 0x00 },// DDR667
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{ 0x00, 0x00, 0x00, 0x00 }// DDR800
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};
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static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] =
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{
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// RxF4 RxF5 RxF6 RxF7
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{ 0x00, 0x00, 0x00, 0x00 },// DDR400
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{ 0x00, 0x00, 0x00, 0x00 },// DDR533
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{ 0x00, 0x00, 0x00, 0x00 },// DDR667
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{ 0x00, 0x00, 0x00, 0x00 }// DDR800
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};
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/*
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DQ/DQS input Capture Control
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modify NB D0F3_Reg:Rx78/Rx79/Rx7A/Rx7B
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*/
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/*static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 }, // 1Rank
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{0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 },
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{0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 }
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};*/
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static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01 }, // 1Rank
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{0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 },
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{0x7B, 0x00, 0x34, 0x34, 0x20, 0x10 }
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};
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static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] =
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{
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// (And NOT) DDR800 DDR667 DDR533 DDR400
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//Reg Mask Value Value Value Value
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{0x79, 0x00, 0x89, 0x89, 0x87, 0x83 }, // 1Rank
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{0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00 },
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{0x8B, 0x00, 0x34, 0x34, 0x20, 0x10 }
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};
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static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] =
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{
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// Rx70 Rx71
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{ 0x00, 0x05 }, // DDR800
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{ 0x00, 0x06 }, // DDR667
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{ 0x00, 0x04 }, // DDR533
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{ 0x00, 0x05 } // DDR400
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};
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static const u8 Fixed_DQSA_3_4_Rank_Table[4][2] =
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{
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// Rx70 Rx71
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{0x00 , 0x04}, // DDR800
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{0x00 , 0x04}, // DDR667
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{0x00 , 0x03}, // DDR533
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{0x00 , 0x04} // DDR400
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};
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@ -1,541 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 One Laptop per Child, Association, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include "console/console.c"
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#include "lib/ramtest.c"
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#include "northbridge/via/vx800/vx800.h"
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#include "cpu/x86/mtrr/earlymtrr.c"
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#include "cpu/x86/bist.h"
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#include "pc80/udelay_io.c"
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#include "lib/delay.c"
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#include "lib/memcpy.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "driving_clk_phase_data.c"
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#include "northbridge/via/vx800/raminit.h"
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#include "northbridge/via/vx800/raminit.c"
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static int acpi_is_wakeup_early_via_vx800(void)
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{
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device_t dev;
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u16 tmp, result;
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print_debug("In acpi_is_wakeup_early_via_vx800\n");
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/* Power management controller */
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_VX855_LPC), 0);
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if (dev == PCI_DEV_INVALID)
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die("Power management controller not found\n");
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/* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */
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pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1);
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/* Enable ACPI access RTC signal gated with PSON. */
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pci_write_config8(dev, 0x81, 0x84);
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tmp = inw(VX800_ACPI_IO_BASE + 0x04);
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result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0;
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print_debug(" boot_mode=");
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print_debug_hex16(result);
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print_debug("\n");
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return result;
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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static void enable_mainboard_devices(void)
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{
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device_t dev;
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uint16_t values;
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print_debug("In enable_mainboard_devices \n");
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/* Enable P2P bridge Header for external PCI bus. */
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dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0);
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pci_write_config8(dev, 0x4f, 0x41);
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}
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static void enable_shadow_ram(void)
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{
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uint8_t shadowreg;
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pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff);
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/* 0xf0000-0xfffff - ACPI tables */
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shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
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shadowreg |= 0x30;
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pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
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/* 0xe0000-0xeffff - elfload? */
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pci_write_config8(PCI_DEV(0, 0, 3), 0x82, 0xff);
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}
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/*
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this table contains the value needed to be set before begin to init dram.
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Note: REV_Bx should be cared when porting a new board!!!!! */
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static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = {
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//VT3409 no pcie
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0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range
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0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie
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//0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control
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// Set ROMSIP value by software
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/*0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pullup Driving = 3
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0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pulldown Driving = 3
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0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pullup Driving = 3
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0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pulldown Driving = 3
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0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21, // Memory I/F timing ctrl
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0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1, // Memory I/F timing ctrl
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0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18, // AGTL+ I/O Circuit
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0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C, // AGTL+ Compensation Status
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0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33, // 2X AGTL+ Auto Compensation Offset
|
||||
0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33, // 4X AGTL+ Auto Compensation Offset
|
||||
0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72, // AGTL Compensation Status
|
||||
0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77, // AGTL Compensation Status
|
||||
0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44, // Input Host Address / Host Strobe Delay Control for HA Group
|
||||
0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22, // Input Host Address / Host Strobe Delay Control for HA Group
|
||||
0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00, // Output Delay Control of PAD for HA Group
|
||||
0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA, // Host Address / Address Clock Output Delay Control (Only for P4 Bus)
|
||||
0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
|
||||
0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
|
||||
0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
|
||||
0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
|
||||
0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44, // Host Data Receiving Strobe Delay Ctrl 1
|
||||
0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44, // Host Data Receiving Strobe Delay Ctrl 2
|
||||
0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00, // Output Delay of PAD for HDSTB
|
||||
0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00, // Output Delay of PAD for HD
|
||||
0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0)
|
||||
0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1)
|
||||
0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2)
|
||||
0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3) */
|
||||
|
||||
|
||||
// CPU Host Bus Control
|
||||
0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
|
||||
//0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
|
||||
0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
|
||||
0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance
|
||||
//0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK
|
||||
0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK
|
||||
0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access
|
||||
//0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2
|
||||
0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2
|
||||
0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1
|
||||
//0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL
|
||||
//0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2
|
||||
0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy
|
||||
0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer
|
||||
0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl
|
||||
// 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3
|
||||
//0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2
|
||||
0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2
|
||||
0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3
|
||||
0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4
|
||||
|
||||
|
||||
// Set APIC and SMRAM
|
||||
0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00, // APIC Related Control
|
||||
0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg
|
||||
0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // End of the table
|
||||
};
|
||||
|
||||
#define USE_VCP 1 //0 means use DVP
|
||||
#define USE_COM1 1
|
||||
#define USE_COM2 0
|
||||
|
||||
#define gCom1Base 0x3f8
|
||||
#define gCom2Base 0x2f8
|
||||
|
||||
void EmbedComInit(void)
|
||||
{
|
||||
u8 ByteVal;
|
||||
u16 ComBase;
|
||||
|
||||
//enable NB multiple function control
|
||||
ByteVal = pci_read_config8(PCI_DEV(0, 0, 0), 0x4f);
|
||||
ByteVal = ByteVal | 0x01;
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, ByteVal);
|
||||
|
||||
//VGA Enable
|
||||
ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA1);
|
||||
ByteVal = ByteVal | 0x80;
|
||||
pci_write_config8(PCI_DEV(0, 0, 3), 0xA1, ByteVal);
|
||||
|
||||
ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA7);
|
||||
ByteVal = ByteVal | 0x08;
|
||||
pci_write_config8(PCI_DEV(0, 0, 3), 0xA7, ByteVal);
|
||||
|
||||
//Enable p2p IO/mem
|
||||
ByteVal = pci_read_config8(PCI_DEV(0, 1, 0), 0x4);
|
||||
ByteVal = ByteVal | 0x07;
|
||||
pci_write_config8(PCI_DEV(0, 1, 0), 0x4, ByteVal);
|
||||
|
||||
//Turn on Graphic chip IO port port access
|
||||
ByteVal = inb(0x3C3);
|
||||
ByteVal = ByteVal | 0x01;
|
||||
outb(ByteVal, 0x3C3);
|
||||
|
||||
//Turn off Graphic chip Register protection
|
||||
outb(0x10, 0x3C4);
|
||||
ByteVal = inb(0x3C5);
|
||||
ByteVal = ByteVal | 0x01;
|
||||
outb(ByteVal, 0x3C5);
|
||||
|
||||
//south module pad share enable 0x3C5.78[7]
|
||||
outb(0x78, 0x3C4);
|
||||
ByteVal = inb(0x3C5);
|
||||
ByteVal = ByteVal | 0x80;
|
||||
outb(ByteVal, 0x3C5);
|
||||
|
||||
//enable UART Function multiplex with DVP or VCP pad D17F0Rx46[7,6]
|
||||
ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0x46);
|
||||
//multiplex with VCP
|
||||
if (USE_VCP == 1)
|
||||
ByteVal = (ByteVal & 0x3F) | 0x40;
|
||||
//multiplex with DVP
|
||||
else
|
||||
ByteVal = (ByteVal & 0x3F) | 0xC0;
|
||||
pci_write_config8(PCI_DEV(0, 17, 0), 0x46, ByteVal);
|
||||
|
||||
//enable embeded com1 and com2 D17F0RxB0[5,4]
|
||||
ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xB0);
|
||||
ByteVal = ByteVal & 0xcf;
|
||||
//multiplex with VCP
|
||||
if (USE_COM1 == 1)
|
||||
ByteVal = ByteVal | 0x10;
|
||||
if (USE_COM2 == 1)
|
||||
ByteVal = ByteVal | 0x20;
|
||||
pci_write_config8(PCI_DEV(0, 17, 0), 0xB0, ByteVal);
|
||||
|
||||
if (USE_COM1 == 1)
|
||||
ComBase = gCom1Base;
|
||||
else
|
||||
ComBase = gCom2Base;
|
||||
|
||||
//noharddrive
|
||||
|
||||
//set embeded com1 IO base = 0x3E8
|
||||
//D17F0RB4
|
||||
//ByteVal = 0xFD;
|
||||
if (USE_COM1 == 1) {
|
||||
ByteVal = (u8) ((gCom1Base >> 3) | 0x80);
|
||||
pci_write_config8(PCI_DEV(0, 17, 0), 0xB4, ByteVal);
|
||||
ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2);
|
||||
ByteVal = (ByteVal & 0xf0) | 0x04;
|
||||
pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal);
|
||||
}
|
||||
//set embeded com2 IO base = 0x2E8
|
||||
//D17F0RB5
|
||||
//ByteVal = 0xDD;
|
||||
if (USE_COM2 == 1) {
|
||||
ByteVal = (u8) ((gCom2Base >> 3) | 0x80);
|
||||
pci_write_config8(PCI_DEV(0, 17, 0), 0xB5, ByteVal);
|
||||
ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2);
|
||||
ByteVal = (ByteVal & 0x0f) | 0x30;
|
||||
pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal);
|
||||
}
|
||||
//no port 80 biger then 0x10
|
||||
|
||||
//disable interrupt
|
||||
ByteVal = inb(ComBase + 3);
|
||||
outb(ByteVal & 0x7F, ComBase + 3);
|
||||
outb(0x00, ComBase + 1);
|
||||
|
||||
//set baudrate
|
||||
ByteVal = inb(ComBase + 3);
|
||||
outb(ByteVal | 0x80, ComBase + 3);
|
||||
outb(0x01, ComBase);
|
||||
outb(0x00, ComBase + 1);
|
||||
|
||||
//set frame fromat
|
||||
ByteVal = inb(ComBase + 3);
|
||||
outb(ByteVal & 0x3F, ComBase + 3);
|
||||
outb(0x03, ComBase + 3);
|
||||
outb(0x00, ComBase + 2);
|
||||
outb(0x00, ComBase + 4);
|
||||
|
||||
//SOutput("Embeded com output\n");
|
||||
//while(1);
|
||||
}
|
||||
|
||||
void main(unsigned long bist)
|
||||
{
|
||||
unsigned cpu_reset = 0;
|
||||
u16 boot_mode;
|
||||
u8 rambits;
|
||||
|
||||
//device_t dev;
|
||||
/* Enable multifunction for northbridge. */
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
|
||||
EmbedComInit();
|
||||
//enable_vx800_serial();
|
||||
//uart_init();
|
||||
|
||||
/* 1. D15F0
|
||||
|
||||
a) RxBAh = 71h
|
||||
|
||||
b) RxBBh = 05h
|
||||
|
||||
c) RxBEh = 71h
|
||||
|
||||
d) RxBFh = 05h
|
||||
|
||||
2. D17F0
|
||||
|
||||
a) RxA0h = 06h
|
||||
|
||||
b) RxA1h = 11h
|
||||
|
||||
c) RxA2h = 27h
|
||||
|
||||
d) RxA3h = 32h
|
||||
|
||||
e) Rx79h = 40h
|
||||
|
||||
f) Rx72h = 27h
|
||||
|
||||
g) Rx73h = 32h
|
||||
*/
|
||||
|
||||
u8 Data8;
|
||||
|
||||
pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBA,
|
||||
PCI_DEVICE_ID_VIA_VX855_IDE);
|
||||
pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBE,
|
||||
PCI_DEVICE_ID_VIA_VX855_IDE);
|
||||
pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA0, PCI_VENDOR_ID_VIA);
|
||||
pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA2,
|
||||
PCI_DEVICE_ID_VIA_VX855_LPC);
|
||||
Data8 = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x79);
|
||||
Data8 &= ~0x40;
|
||||
Data8 |= 0x40;
|
||||
pci_write_config8(PCI_DEV(0, 0x11, 0), 0x79, Data8);
|
||||
pci_write_config16(PCI_DEV(0, 0x11, 0), 0x72,
|
||||
PCI_DEVICE_ID_VIA_VX855_LPC);
|
||||
|
||||
console_init(); //there are to function defination of console_init(), while the src/archi386/lib is the right one
|
||||
|
||||
/* decide if this is a s3 wakeup or a normal boot */
|
||||
boot_mode = acpi_is_wakeup_early_via_vx800();
|
||||
/*add this, to transfer "cpu restart" to "cold boot"
|
||||
When this boot is not a S3 resume, and PCI registers had been written,
|
||||
then this must be a cpu restart(result of os reboot cmd). so we need a real "cold boot". */
|
||||
if ((boot_mode != 3)
|
||||
&& (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) {
|
||||
outb(6, 0xcf9);
|
||||
}
|
||||
|
||||
/*x86 cold boot I/O cmd */
|
||||
enable_smbus();
|
||||
//smbus_fixup(&ctrl);// this fix does help vx800!, but vx855 no need this
|
||||
|
||||
if (bist == 0) {
|
||||
// CAR need mtrr untill mem is ok, so i disable this early_mtrr_init();
|
||||
//print_debug("doing early_mtrr\n");
|
||||
//early_mtrr_init();
|
||||
}
|
||||
|
||||
/* Halt if there was a built-in self test failure. */
|
||||
report_bist_failure(bist);
|
||||
|
||||
print_debug("Enabling mainboard devices\n");
|
||||
enable_mainboard_devices();
|
||||
|
||||
u8 Data;
|
||||
device_t device;
|
||||
/* Get NB Chip revision from D0F4RxF6, revision will be used in via_pci_inittable */
|
||||
device = PCI_DEV(0, 0, 4);
|
||||
Data = pci_read_config8(device, 0xf6);
|
||||
print_debug("NB chip revision =");
|
||||
print_debug_hex8(Data);
|
||||
print_debug("\n");
|
||||
/* make NB ready before draminit */
|
||||
via_pci_inittable(Data, mNbStage1InitTbl);
|
||||
|
||||
/*add this.
|
||||
When resume from s3, draminit is skiped, so need to recovery any PCI register related to draminit.
|
||||
and d0f3 didnt lost its Power during whole s3 time, so any register not belongs to d0f3 need to be recoveried . */
|
||||
#if 1
|
||||
if (boot_mode == 3) {
|
||||
u8 i;
|
||||
u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
|
||||
DRAM_SYS_ATTR DramAttr;
|
||||
|
||||
print_debug("This is a S3 wakeup\n");
|
||||
|
||||
memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR));
|
||||
/*Step1 DRAM Detection; DDR1 or DDR2; Get SPD Data; Rank Presence;64 or 128bit; Unbuffered or registered; 1T or 2T */
|
||||
DRAMDetect(&DramAttr);
|
||||
|
||||
/*begin to get ram size, 43,42 41 40 contains the end address of last rank in ddr2-slot */
|
||||
device = PCI_DEV(0, 0, 3);
|
||||
for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
|
||||
rambits = pci_read_config8(device, ramregs[i]);
|
||||
if (rambits != 0)
|
||||
break;
|
||||
}
|
||||
|
||||
DRAMDRDYSetting(&DramAttr);
|
||||
|
||||
Data = 0x80; // this value is same with dev_init.c
|
||||
pci_write_config8(PCI_DEV(0, 0, 4), 0xa3, Data);
|
||||
pci_write_config8(PCI_DEV(0, 17, 7), 0x60, rambits << 2);
|
||||
Data = pci_read_config8(MEMCTRL, 0x88);
|
||||
pci_write_config8(PCI_DEV(0, 17, 7), 0xE5, Data);
|
||||
|
||||
DRAMRegFinalValue(&DramAttr); // I just copy this function from draminit to here!
|
||||
SetUMARam(); // I just copy this function from draminit to here!
|
||||
print_debug("Resume from S3, RAM init was ignored\n");
|
||||
} else {
|
||||
ddr2_ram_setup();
|
||||
ram_check(0, 640 * 1024);
|
||||
}
|
||||
#endif
|
||||
//ddr2_ram_setup();
|
||||
/*this line is the same with cx700 port . */
|
||||
enable_shadow_ram();
|
||||
|
||||
/*
|
||||
For coreboot most time of S3 resume is the same as normal boot, so some memory area under 1M become dirty,
|
||||
so before this happen, I need to backup the content of mem to top-mem.
|
||||
I will reserve the 1M top-men in LBIO table in coreboot_table.c and recovery the content of 1M-mem in wakeup.c
|
||||
*/
|
||||
#if PAYLOAD_IS_SEABIOS==1 //
|
||||
if (boot_mode == 3) {
|
||||
/* some idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html
|
||||
I want move the 1M data, I have to set some MTRRs myself. */
|
||||
/* setting mtrr before back memory save s3 resume time about 0.14 seconds */
|
||||
/*because CAR stack use cache, and here to use cache , must be careful,
|
||||
1 during these mtrr code, must no function call, (after this mtrr, I think it should be ok to use function)
|
||||
2 before stack switch, no use variable that have value set before this
|
||||
3 due to 2, take care of "cpu_reset", I directlly set it to ZERO.
|
||||
*/
|
||||
u32 memtop = *(u32 *) WAKE_MEM_INFO;
|
||||
u32 memtop1 = *(u32 *) WAKE_MEM_INFO - 0x100000;
|
||||
u32 memtop2 = *(u32 *) WAKE_MEM_INFO - 0x200000;
|
||||
u32 memtop3 =
|
||||
*(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000;
|
||||
u32 memtop4 =
|
||||
*(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000 +
|
||||
0xe0000;
|
||||
/* __asm__ volatile (
|
||||
"movl $0x204, %%ecx\n\t"
|
||||
"xorl %%edx, %%edx\n\t"
|
||||
"movl %0,%%eax\n\t"
|
||||
"orl $(0 | 6), %%eax\n\t"
|
||||
"wrmsr\n\t"
|
||||
|
||||
"movl $0x205, %%ecx\n\t"
|
||||
"xorl %%edx, %%edx\n\t"
|
||||
"movl $0x100000,%%eax\n\t"
|
||||
"decl %%eax\n\t"
|
||||
"notl %%eax\n\t"
|
||||
"orl $(0 | 0x800), %%eax\n\t"
|
||||
"wrmsr\n\t"
|
||||
::"g"(memtop2)
|
||||
);
|
||||
__asm__ volatile (
|
||||
"movl $0x206, %%ecx\n\t"
|
||||
"xorl %%edx, %%edx\n\t"
|
||||
"movl %0,%%eax\n\t"
|
||||
"orl $(0 | 6), %%eax\n\t"
|
||||
"wrmsr\n\t"
|
||||
|
||||
"movl $0x207, %%ecx\n\t"
|
||||
"xorl %%edx, %%edx\n\t"
|
||||
"movl $0x100000,%%eax\n\t"
|
||||
"decl %%eax\n\t"
|
||||
"notl %%eax\n\t"
|
||||
"orl $(0 | 0x800), %%eax\n\t"
|
||||
"wrmsr\n\t"
|
||||
::"g"(memtop1)
|
||||
);
|
||||
__asm__ volatile (
|
||||
"movl $0x208, %ecx\n\t"
|
||||
"xorl %edx, %edx\n\t"
|
||||
"movl $0,%eax\n\t"
|
||||
"orl $(0 | 6), %eax\n\t"
|
||||
"wrmsr\n\t"
|
||||
|
||||
"movl $0x209, %ecx\n\t"
|
||||
"xorl %edx, %edx\n\t"
|
||||
"movl $0x100000,%eax\n\t"
|
||||
"decl %eax\n\t"
|
||||
"notl %eax\n\t"
|
||||
"orl $(0 | 0x800), %eax\n\t"
|
||||
"wrmsr\n\t"
|
||||
);
|
||||
*/
|
||||
// WAKE_MEM_INFO is inited in get_set_top_available_mem in tables.c
|
||||
// these two memcpy not not be enabled if set the MTRR around this two lines.
|
||||
/*__asm__ volatile (
|
||||
"movl $0, %%esi\n\t"
|
||||
"movl %0, %%edi\n\t"
|
||||
"movl $0xa0000, %%ecx\n\t"
|
||||
"shrl $2, %%ecx\n\t"
|
||||
"rep movsd\n\t"
|
||||
::"g"(memtop3)
|
||||
);
|
||||
__asm__ volatile (
|
||||
"movl $0xe0000, %%esi\n\t"
|
||||
"movl %0, %%edi\n\t"
|
||||
"movl $0x20000, %%ecx\n\t"
|
||||
"shrl $2, %%ecx\n\t"
|
||||
"rep movsd\n\t"
|
||||
::"g"(memtop4)
|
||||
);*/
|
||||
print_debug("copy memory to high memory to protect s3 wakeup vector code \n"); //this can have function call, because no variable used before this
|
||||
memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) -
|
||||
64 * 1024 - 0x100000),
|
||||
(unsigned char *) 0, 0xa0000);
|
||||
memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) -
|
||||
64 * 1024 - 0x100000 + 0xe0000),
|
||||
(unsigned char *) 0xe0000, 0x20000);
|
||||
|
||||
/* restore the MTRR previously modified. */
|
||||
/* __asm__ volatile (
|
||||
"wbinvd\n\t"
|
||||
"xorl %edx, %edx\n\t"
|
||||
"xorl %eax, %eax\n\t"
|
||||
"movl $0x204, %ecx\n\t"
|
||||
"wrmsr\n\t"
|
||||
"movl $0x205, %ecx\n\t"
|
||||
"wrmsr\n\t"
|
||||
"movl $0x206, %ecx\n\t"
|
||||
"wrmsr\n\t"
|
||||
"movl $0x207, %ecx\n\t"
|
||||
"wrmsr\n\t"
|
||||
"movl $0x208, %ecx\n\t"
|
||||
"wrmsr\n\t"
|
||||
"movl $0x209, %ecx\n\t"
|
||||
"wrmsr\n\t"
|
||||
);*/
|
||||
}
|
||||
#endif
|
||||
}
|
||||
Loading…
Reference in New Issue