nb/intel/x4x: Use parallel MP init

Use parallel MP init code to initialize all AP's.

Also remove guards around CPU code where all platforms now use
parallel MP init.

This also removes the code required on lapic init path for
model_6fx, model_1017x and model_f4x as all platforms now use the
parallel MP code.

Tested on Intel DG41WV, shaves off about 90ms on a quad core.

Change-Id: Id5a2729f5bf6b525abad577e63d7953ae6640921
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25601
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/model_1067x/model_1067x_init.c

@@ -19,13 +19,10 @@
 #include <device/device.h>
 #include <string.h>
 #include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/lapic.h>
-#include <cpu/intel/microcode.h>
 #include <cpu/intel/speedstep.h>
-#include <cpu/intel/hyperthreading.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
 #include <cpu/intel/smm/gen1/smi.h>
@@ -280,20 +277,10 @@ static void model_1067x_init(struct device *cpu)
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
-	/* Update the microcode */
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP))
-		intel_update_microcode_from_cbfs();
-
 	/* Print processor name */
 	fill_processor_name(processor_name);
 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
-	/* Setup MTRRs */
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP)) {
-		x86_setup_mtrrs();
-		x86_mtrr_check();
-	}
-
 	/* Enable the local CPU APICs */
 	setup_lapic();
 
@@ -318,10 +305,6 @@ static void model_1067x_init(struct device *cpu)
 
 	/* PIC thermal sensor control */
 	configure_pic_thermal_sensors(tm2, quad);
-
-	/* Start up my CPU siblings */
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP))
-		intel_sibling_init(cpu);
 }
 
 static struct device_operations cpu_dev_ops = {

src/cpu/intel/model_6fx/model_6fx_init.c

@@ -18,11 +18,8 @@
 #include <device/device.h>
 #include <string.h>
 #include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
-#include <cpu/intel/hyperthreading.h>
-#include <cpu/intel/microcode.h>
 #include <cpu/intel/speedstep.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
@@ -132,20 +129,10 @@ static void model_6fx_init(struct device *cpu)
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
-	/* Update the microcode */
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP))
-		intel_update_microcode_from_cbfs();
-
 	/* Print processor name */
 	fill_processor_name(processor_name);
 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
-	/* Setup MTRRs */
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP)) {
-		x86_setup_mtrrs();
-		x86_mtrr_check();
-	}
-
 	/* Setup Page Attribute Tables (PAT) */
 	// TODO set up PAT
 
@@ -163,10 +150,6 @@ static void model_6fx_init(struct device *cpu)
 
 	/* PIC thermal sensor control */
 	configure_pic_thermal_sensors();
-
-	/* Start up my CPU siblings */
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP))
-		intel_sibling_init(cpu);
 }
 
 static struct device_operations cpu_dev_ops = {

src/cpu/intel/model_f4x/model_f4x_init.c

@@ -13,10 +13,7 @@
 
 #include <device/device.h>
 #include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
 #include <cpu/x86/lapic.h>
-#include <cpu/intel/microcode.h>
-#include <cpu/intel/hyperthreading.h>
 #include <cpu/x86/cache.h>
 
 static void model_f4x_init(struct device *cpu)
@@ -24,21 +21,8 @@ static void model_f4x_init(struct device *cpu)
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) {
-		/* MTRRs are shared between threads */
-		x86_setup_mtrrs();
-		x86_mtrr_check();
-
-		/* Update the microcode */
-		intel_update_microcode_from_cbfs();
-	}
-
 	/* Enable the local CPU APICs */
 	setup_lapic();
-
-	/* Start up my CPU siblings */
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP))
-		intel_sibling_init(cpu);
 };
 
 static struct device_operations cpu_dev_ops = {

src/mainboard/asrock/g41c-gs/cmos.layout

@@ -56,7 +56,6 @@ entries
 409          2       e       7        power_on_after_fail
 
 # coreboot config options: cpu
-#424          1       e       2        hyper_threading
 #425        7       r       0        unused
 
 # coreboot config options: northbridge

src/mainboard/foxconn/g41s-k/cmos.layout

@@ -56,7 +56,6 @@ entries
 409          2       e       7        power_on_after_fail
 
 # coreboot config options: cpu
-#424          1       e       2        hyper_threading
 #425        7       r       0        unused
 
 # coreboot config options: northbridge

src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout

@@ -57,7 +57,6 @@ entries
 409          2       e       7        power_on_after_fail
 
 # coreboot config options: cpu
-#424          1       e       2        hyper_threading
 #425        7       r       0        unused
 
 # coreboot config options: northbridge

src/northbridge/intel/x4x/Kconfig

@@ -29,6 +29,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select POSTCAR_STAGE
 	select POSTCAR_CONSOLE
 	select SMM_TSEG
+	select PARALLEL_MP
 
 config CBFS_SIZE
 	hex

src/northbridge/intel/x4x/northbridge.c

@@ -182,26 +182,6 @@ void northbridge_write_smram(u8 smram)
 	pci_write_config8(dev, D0F0_SMRAM, smram);
 }
 
-/*
- * Really doesn't belong here but will go away with parallel mp init,
- * so let it be here for a while...
- */
-int cpu_get_apic_id_map(int *apic_id_map)
-{
-	unsigned int i;
-
-	/* Logical processors (threads) per core */
-	const struct cpuid_result cpuid1 = cpuid(1);
-	/* Read number of cores. */
-	const char cores = (cpuid1.ebx >> 16) & 0xf;
-
-	/* TODO in parallel MP cpuid(1).ebx */
-	for (i = 0; i < cores; i++)
-		apic_id_map[i] = i;
-
-	return cores;
-}
-
 static struct device_operations pci_domain_ops = {
 	.read_resources   = mch_domain_read_resources,
 	.set_resources    = mch_domain_set_resources,
@@ -215,7 +195,7 @@ static struct device_operations pci_domain_ops = {
 
 static void cpu_bus_init(struct device *dev)
 {
-	initialize_cpus(dev->link_list);
+	bsp_init_and_start_aps(dev->link_list);
 }
 
 static struct device_operations cpu_bus_ops = {

src/southbridge/intel/i82801jx/lpc.c

@@ -392,10 +392,6 @@ static void i82801jx_lock_smm(struct device *dev)
 		printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n");
 		outb(APM_CNT_ACPI_ENABLE, APM_CNT);
 	}
-	/* Don't allow evil boot loaders, kernels, or
-	 * userspace applications to deceive us:
-	 */
-	smm_lock();
 
 #if TEST_SMM_FLASH_LOCKDOWN
 	/* Now try this: */