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mb/google/fizz: skip reading SPD data when DUT resumes from S3 

This patch skips SPD data reading when system resumes from S3 since
MRC cahce is adopted and validated in fsp_memory_init.

BUG=b:67021596
TEST=Run suspend/resume on Fizz and make sure the systems are
	working well when system resumes from S3. Checked dmidecode
	information and SMBIOS type 17 data is the same with cold
	boot.

Change-Id: I1692fca8456290d1471973b746537b5fec504e03
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Gaggery Tsai 2017-10-12 17:22:22 +08:00 committed by Aaron Durbin
parent caca9c7c62
commit c869cd2f44
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/google/fizz/romstage.c
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@ -22,11 +22,16 @@
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
/* Rcomp resistor */
const u16 rcomp_resistor[] = { 200, 81, 162 };
/* Rcomp target */
const u16 rcomp_target[] = { 100, 40, 40, 23, 40 };
/* SPD was saved in S0/S5 path, skips it when resumes from S3 */
if (arch_upd->BootMode == FSP_BOOT_ON_S3_RESUME)
return;
memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor));
memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target));