GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test 

The XTAL 26MHz test failed on krabby, so we adjust RTC capid from
default value 0x88 to 0xC0 for MT8186. We also add a new log message
to show the capid value which is read from MT6366.

This implementation is according to chapter 5.13 in MT8186 Functional
Specification.

BUG=b:218439447
TEST=set capid to 0xc0.
TEST=XTAL 26MHz test passed.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Rex-BC Chen 2022-02-11 16:10:05 +08:00 committed by Felix Held
parent 025fb17372
commit c89f252608
2 changed files with 15 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/mediatek/mt8186/include/soc/rtc.h
View File

@ -143,6 +143,7 @@ enum {
PMIC_RG_DCXO_CW00 = 0x0788, PMIC_RG_DCXO_CW00 = 0x0788,
PMIC_RG_DCXO_CW00_CLR = 0x078C, PMIC_RG_DCXO_CW00_CLR = 0x078C,
PMIC_RG_DCXO_CW02 = 0x0790, PMIC_RG_DCXO_CW02 = 0x0790,
PMIC_RG_DCXO_CW03 = 0x0794,
PMIC_RG_DCXO_CW07 = 0x079A, PMIC_RG_DCXO_CW07 = 0x079A,
PMIC_RG_DCXO_CW09 = 0x079E, PMIC_RG_DCXO_CW09 = 0x079E,
PMIC_RG_DCXO_CW11 = 0x07A2, PMIC_RG_DCXO_CW11 = 0x07A2,

14
src/soc/mediatek/mt8186/rtc.c
View File

@ -13,6 +13,8 @@
#include <soc/pmic_wrap.h> #include <soc/pmic_wrap.h>
#include <timer.h> #include <timer.h>
#define MT8186_RTC_DXCO_CAPID 0xC0
/* Initialize RTC setting of using DCXO clock */ /* Initialize RTC setting of using DCXO clock */
static bool rtc_enable_dcxo(void) static bool rtc_enable_dcxo(void)
{ {
@ -231,6 +233,16 @@ static void mt6366_dcxo_disable_unused(void)
rtc_write(PMIC_RG_DCXO_CW23, 0x0052); rtc_write(PMIC_RG_DCXO_CW23, 0x0052);
} }
static void rtc_set_capid(u16 capid)
{
u16 read_capid;
rtc_write(PMIC_RG_DCXO_CW03, 0xFF00 | capid);
rtc_read(PMIC_RG_DCXO_CW03, &read_capid);
rtc_info("read back capid: %#x\n", read_capid & 0xFF);
}
/* Check RTC Initialization */ /* Check RTC Initialization */
int rtc_init(int recover) int rtc_init(int recover)
{ {
@ -337,6 +349,8 @@ static void dcxo_init(void)
rtc_write(PMIC_RG_DCXO_CW09, 0x408F); rtc_write(PMIC_RG_DCXO_CW09, 0x408F);
mdelay(5); mdelay(5);
rtc_set_capid(MT8186_RTC_DXCO_CAPID);
mt6366_dcxo_disable_unused(); mt6366_dcxo_disable_unused();
} }