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cpu/*: Drop PARALLEL_MP leftovers 

These symbols and codepaths are unused now so drop them.

Change-Id: I7c46c36390f116f8f8920c06e539075e60c7118c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69361
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2022-11-08 06:49:12 +01:00 committed by Kyösti Mälkki
parent 753827ef33
commit c8a20b9d3b
7 changed files with 1 additions and 127 deletions
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1
src/cpu/intel/hyperthreading/Makefile.inc
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@ -1 +0,0 @@
ramstage-y += intel_sibling.c

65
src/cpu/intel/hyperthreading/intel_sibling.c
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@ -1,65 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/intel/hyperthreading.h>
#include <device/device.h>
#include <option.h>
/* Intel hyper-threading requires serialized CPU init. */
static int first_time = 1;
static int disable_siblings = !CONFIG(LOGICAL_CPUS);
void intel_sibling_init(struct device *cpu)
{
unsigned int i, siblings;
struct cpuid_result result;
/* On the bootstrap processor see if I want sibling cpus enabled */
if (first_time) {
first_time = 0;
disable_siblings = get_uint_option("hyper_threading", disable_siblings);
}
result = cpuid(1);
/* Is hyperthreading supported */
if (!(result.edx & (1 << 28)))
return;
/* See how many sibling cpus we have */
siblings = (result.ebx >> 16) & 0xff;
if (siblings < 1)
siblings = 1;
printk(BIOS_DEBUG, "CPU: %u %d siblings\n",
cpu->path.apic.apic_id,
siblings);
/* See if I am a sibling cpu */
if (cpu->path.apic.apic_id & (siblings - 1)) {
if (disable_siblings)
cpu->enabled = 0;
return;
}
/* I am the primary CPU start up my siblings */
for (i = 1; i < siblings; i++) {
struct device_path cpu_path;
struct device *new;
/* Build the CPU device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = cpu->path.apic.apic_id + i;
/* Allocate new CPU device structure iff sibling CPU
* was not in static device tree.
*/
new = alloc_find_dev(cpu->bus, &cpu_path);
if (!new)
continue;
printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
cpu->path.apic.apic_id,
new->path.apic.apic_id);
}
}

1
src/cpu/intel/model_f3x/Makefile.inc
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@ -1,6 +1,5 @@
ramstage-y += model_f3x_init.c ramstage-y += model_f3x_init.c
subdirs-y += ../hyperthreading
subdirs-y += ../smm/gen1 subdirs-y += ../smm/gen1
ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c

14
src/cpu/intel/model_f3x/model_f3x_init.c
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@ -2,7 +2,6 @@
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include <cpu/intel/common/common.h> #include <cpu/intel/common/common.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/intel/microcode.h> #include <cpu/intel/microcode.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
@ -12,19 +11,6 @@ static void model_f3x_init(struct device *cpu)
{ {
/* Turn on caching if we haven't already */ /* Turn on caching if we haven't already */
enable_cache(); enable_cache();
if (!CONFIG(PARALLEL_MP) && !intel_ht_sibling()) {
/* MTRRs are shared between threads */
x86_setup_mtrrs();
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode_from_cbfs();
}
/* Start up my CPU siblings */
if (!CONFIG(PARALLEL_MP))
intel_sibling_init(cpu);
}; };
static struct device_operations cpu_dev_ops = { static struct device_operations cpu_dev_ops = {

4
src/cpu/x86/Kconfig.debug_cpu
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@ -10,8 +10,4 @@ config DEBUG_CAR
config DISPLAY_MTRRS config DISPLAY_MTRRS
bool "Display intermediate MTRR settings" bool "Display intermediate MTRR settings"
config DEBUG_SMM_RELOCATION
bool "Debug SMM relocation code"
depends on HAVE_SMI_HANDLER && SMM_ASEG
endif # ARCH_X86 endif # ARCH_X86

9
src/include/cpu/intel/hyperthreading.h
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@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef CPU_INTEL_HYPERTHREADING_H
#define CPU_INTEL_HYPERTHREADING_H
struct device;
void intel_sibling_init(struct device *cpu);
#endif /* CPU_INTEL_HYPERTHREADING_H */

32
src/mainboard/emulation/qemu-i440fx/northbridge.c
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@ -254,45 +254,13 @@ void mp_init_cpus(struct bus *cpu_bus)
static void cpu_bus_init(struct device *dev) static void cpu_bus_init(struct device *dev)
{ {
if (CONFIG(PARALLEL_MP))
mp_cpu_bus_init(dev); mp_cpu_bus_init(dev);
else
initialize_cpus(dev->link_list);
}
static void cpu_bus_scan(struct device *bus)
{
unsigned int max_cpus = fw_cfg_max_cpus();
struct device *cpu;
int i;
if (max_cpus == 0)
return;
/*
* Do not install more CPUs than supported by coreboot.
* This will cause a buffer overflow where fixed arrays of CONFIG_MAX_CPUS
* are used and might result in a boot failure.
*/
max_cpus = MIN(max_cpus, CONFIG_MAX_CPUS);
/*
* TODO: This only handles the simple "qemu -smp $nr" case
* correctly. qemu also allows to specify the number of
* cores, threads & sockets.
*/
printk(BIOS_INFO, "QEMU: max_cpus is %d\n", max_cpus);
for (i = 0; i < max_cpus; i++) {
cpu = add_cpu_device(bus->link_list, i, 1);
if (cpu)
set_cpu_topology(cpu, 1, 0, i, 0);
}
} }
static struct device_operations cpu_bus_ops = { static struct device_operations cpu_bus_ops = {
.read_resources = noop_read_resources, .read_resources = noop_read_resources,
.set_resources = noop_set_resources, .set_resources = noop_set_resources,
.init = cpu_bus_init, .init = cpu_bus_init,
.scan_bus = cpu_bus_scan,
}; };
static void northbridge_enable(struct device *dev) static void northbridge_enable(struct device *dev)