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mb/google/guybrush: Enable PCIe L1 Substates 

This change enables L1.1 and L1.2 on all real Guybrush PCIe devices.

BUG=b:188123142
TEST=Boot to ChromeOS and verify L1SS are functional by dumping the
settings with "lspci -vv". Leave system on for 20 minutes and no hang.
Also perform 20 reboots and suspend operations

Cq-Depend: chrome-internal:4012927
Change-Id: I40d19be78bfcb9a30fb59f48530a4413dadbefbc
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Matt Papageorge 2021-05-14 14:08:53 -05:00 committed by Felix Held
parent 77fb9a0bb2
commit c8f926adda
2 changed files with 9 additions and 0 deletions
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1
src/mainboard/google/guybrush/Kconfig
View File

@ -37,6 +37,7 @@ config BOARD_SPECIFIC_OPTIONS
select PCIEXP_ASPM select PCIEXP_ASPM
select PCIEXP_CLK_PM select PCIEXP_CLK_PM
select PCIEXP_COMMON_CLOCK select PCIEXP_COMMON_CLOCK
select PCIEXP_L1_SUB_STATE
select PSP_DISABLE_POSTCODES select PSP_DISABLE_POSTCODES
select SOC_AMD_CEZANNE select SOC_AMD_CEZANNE
select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF

8
src/mainboard/google/guybrush/port_descriptors.c
View File

@ -16,6 +16,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.device_number = PCI_SLOT(WLAN_DEVFN), .device_number = PCI_SLOT(WLAN_DEVFN),
.function_number = PCI_FUNC(WLAN_DEVFN), .function_number = PCI_FUNC(WLAN_DEVFN),
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true, .turn_off_unused_lanes = true,
.clk_req = CLK_REQ0, .clk_req = CLK_REQ0,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
@ -28,6 +30,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.device_number = PCI_SLOT(SD_DEVFN), .device_number = PCI_SLOT(SD_DEVFN),
.function_number = PCI_FUNC(SD_DEVFN), .function_number = PCI_FUNC(SD_DEVFN),
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true, .turn_off_unused_lanes = true,
.clk_req = CLK_REQ1, .clk_req = CLK_REQ1,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
@ -40,6 +44,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.device_number = PCI_SLOT(WWAN_DEVFN), .device_number = PCI_SLOT(WWAN_DEVFN),
.function_number = PCI_FUNC(WWAN_DEVFN), .function_number = PCI_FUNC(WWAN_DEVFN),
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true, .turn_off_unused_lanes = true,
.clk_req = CLK_REQ2, .clk_req = CLK_REQ2,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
@ -52,6 +58,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.device_number = PCI_SLOT(NVME_DEVFN), .device_number = PCI_SLOT(NVME_DEVFN),
.function_number = PCI_FUNC(NVME_DEVFN), .function_number = PCI_FUNC(NVME_DEVFN),
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true, .turn_off_unused_lanes = true,
.clk_req = CLK_REQ3, .clk_req = CLK_REQ3,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}