GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/stoneyridge: Convert 48Mhz enable to read/write32 

Use the appropriate read32() and write32() calls.  Remove unnecessary
cast.

Change-Id: Ib5430bdb30844d3508a09ddb77a969c0628f6c7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Marshall Dawson 2017-07-13 12:51:19 -06:00 committed by Martin Roth
parent 7bf860ffed
commit c95d6ffa7c
1 changed files with 4 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/soc/amd/stoneyridge/early_setup.c
View File

@ -224,18 +224,17 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
void hudson_clk_output_48Mhz(void)
{
u32 data, *memptr;
u32 ctrl;
/*
* Enable the X14M_25M_48M_OSC pin and leaving it at it's default so
* 48Mhz will be on ball AP13 (FT3b package)
*/
memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40);
data = *memptr;
ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40));
/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
data &= (u32)~(1<<2);
*memptr = data;
ctrl &= ~(1<<2);
write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl);
}
static uintptr_t hudson_spibase(void)