intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers
Add registers that are relevant for the case intrusion detection functionality. Intel documents: 332691-003EN, 335193-006, 341081-001, ... Change-Id: If12d21e8e6721abb877cbbfbbba8f0127a86d96b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
parent
7f9ceef51b
commit
c96f802f7f
|
@ -21,8 +21,13 @@
|
|||
#define TCO_TIMEOUT (1 << 3)
|
||||
#define TCO2_STS 0x06
|
||||
#define TCO_STS_SECOND_TO (1 << 1)
|
||||
#define TCO_INTRD_DET (1 << 0)
|
||||
#define TCO1_CNT 0x08
|
||||
#define TCO_LOCK (1 << 12)
|
||||
#define TCO_TMR_HLT (1 << 11)
|
||||
#define TCO2_CNT 0x0A
|
||||
#define TCO_INTRD_SEL_MASK (3 << 1)
|
||||
#define TCO_INTRD_SEL_SMI (1 << 2)
|
||||
#define TCO_INTRD_SEL_INT (1 << 1)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -24,9 +24,14 @@
|
|||
#define TCO_TIMEOUT (1 << 3)
|
||||
#define TCO2_STS 0x06
|
||||
#define TCO_STS_SECOND_TO (1 << 1)
|
||||
#define TCO_INTRD_DET (1 << 0)
|
||||
#define TCO1_CNT 0x08
|
||||
#define TCO_LOCK (1 << 12)
|
||||
#define TCO_TMR_HLT (1 << 11)
|
||||
#define TCO2_CNT 0x0A
|
||||
#define TCO_INTRD_SEL_MASK (3 << 1)
|
||||
#define TCO_INTRD_SEL_SMI (1 << 2)
|
||||
#define TCO_INTRD_SEL_INT (1 << 1)
|
||||
|
||||
/*
|
||||
* Default slave address value for PCH. This value is set to match default
|
||||
|
|
|
@ -21,9 +21,14 @@
|
|||
#define TCO_TIMEOUT (1 << 3)
|
||||
#define TCO2_STS 0x06
|
||||
#define TCO_STS_SECOND_TO (1 << 1)
|
||||
#define TCO_INTRD_DET (1 << 0)
|
||||
#define TCO1_CNT 0x08
|
||||
#define TCO_LOCK (1 << 12)
|
||||
#define TCO_TMR_HLT (1 << 11)
|
||||
#define TCO2_CNT 0x0A
|
||||
#define TCO_INTRD_SEL_MASK (3 << 1)
|
||||
#define TCO_INTRD_SEL_SMI (1 << 2)
|
||||
#define TCO_INTRD_SEL_INT (1 << 1)
|
||||
|
||||
/*
|
||||
* Default slave address value for PCH. This value is set to match default
|
||||
|
|
|
@ -23,10 +23,15 @@
|
|||
#define TCO1_STS 0x04
|
||||
#define TCO_TIMEOUT (1 << 3)
|
||||
#define TCO2_STS 0x06
|
||||
#define TCO_STS_SECOND_TO 0x02
|
||||
#define TCO_STS_SECOND_TO (1 << 1)
|
||||
#define TCO_INTRD_DET (1 << 0)
|
||||
#define TCO1_CNT 0x08
|
||||
#define TCO_LOCK (1 << 12)
|
||||
#define TCO_TMR_HLT (1 << 11)
|
||||
#define TCO2_CNT 0x0A
|
||||
#define TCO_INTRD_SEL_MASK (3 << 1)
|
||||
#define TCO_INTRD_SEL_SMI (1 << 2)
|
||||
#define TCO_INTRD_SEL_INT (1 << 1)
|
||||
|
||||
/* SMBus I/O bits. */
|
||||
#define SMBUS_SLAVE_ADDR 0x24
|
||||
|
|
|
@ -29,9 +29,14 @@
|
|||
#define TCO_TIMEOUT (1 << 3)
|
||||
#define TCO2_STS 0x06
|
||||
#define TCO_STS_SECOND_TO (1 << 1)
|
||||
#define TCO_INTRD_DET (1 << 0)
|
||||
#define TCO1_CNT 0x08
|
||||
#define TCO_LOCK (1 << 12)
|
||||
#define TCO_TMR_HLT (1 << 11)
|
||||
#define TCO2_CNT 0x0A
|
||||
#define TCO_INTRD_SEL_MASK (3 << 1)
|
||||
#define TCO_INTRD_SEL_SMI (1 << 2)
|
||||
#define TCO_INTRD_SEL_INT (1 << 1)
|
||||
|
||||
/*
|
||||
* Default slave address value for PCH. This value is set to match default
|
||||
|
|
Loading…
Reference in New Issue