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mb/google/brya/var/anahera{4es}: Set tcc_offset value to 3 

The anahera thermal team has determined that the TCC circuit trip
temperature should be set to 97C, therefore, because the offset
is subtracted from 100C, set the `tcc_offset` register in the
devicetree to 3.

BUG=b:214088543
TEST=build and verified by thermal team

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I25b8a3d9e5fe28e9497b735c50a09994092b2243
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Wisley Chen 2022-01-11 17:59:15 +06:00 committed by Tim Wawrzynczak
parent a99355376b
commit c98df1478b
2 changed files with 2 additions and 0 deletions
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1
src/mainboard/google/brya/variants/anahera/overridetree.cb
View File

@ -62,6 +62,7 @@ chip soc/intel/alderlake
.data_hold_time_ns = 50,
},
}"
register "tcc_offset" = "3" # TCC of 97C
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port

1
src/mainboard/google/brya/variants/anahera4es/overridetree.cb
View File

@ -54,6 +54,7 @@ chip soc/intel/alderlake
.speed = I2C_SPEED_FAST,
},
}"
register "tcc_offset" = "3" # TCC of 97C
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port