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Revert "src/drivers/intel/wifi: Add a W/A for Intel ThP2 9260" 

This reverts commit 3afb84a245.

Reason for revert: This is causing issues with the PCIe link
and the system is unable to enter S0ix.  Until it can be fixed
in coreboot revert the change here that is not working properly.

BUG=b:124264120

Change-Id: Ia20da9ab560ca35950b4a916667f51e0f541b382
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31559
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Duncan Laurie 2019-02-22 01:14:23 +00:00
parent 4323175818
commit c98e36fec5
1 changed files with 0 additions and 25 deletions
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25
src/drivers/intel/wifi/wifi.c
View File

@ -255,34 +255,9 @@ static const char *intel_wifi_acpi_name(const struct device *dev)
}
#endif
static void pci_dev_apply_quirks(struct device *dev)
{
unsigned int cap;
uint16_t val;
struct device *root = dev->bus->dev;
switch (dev->device) {
case PCI_DEVICE_ID_TP_9260_SERIES_WIFI:
cap = pci_find_capability(root, PCI_CAP_ID_PCIE);
/* Check the LTR for root port and enable it */
if (cap) {
val = pci_read_config16(root, cap +
PCI_EXP_DEV_CAP2_OFFSET);
if (val & LTR_MECHANISM_SUPPORT) {
val = pci_read_config16(root, cap +
PCI_EXP_DEV_CTL_STS2_CAP_OFFSET);
val |= LTR_MECHANISM_EN;
pci_write_config16(root, cap +
PCI_EXP_DEV_CTL_STS2_CAP_OFFSET, val);
}
}
}
}
static void wifi_pci_dev_init(struct device *dev)
{
pci_dev_init(dev);
pci_dev_apply_quirks(dev);
if (IS_ENABLED(CONFIG_ELOG)) {
uint32_t val;