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make early_mtrr_init() invisible for cache as ram targets as it breaks them. 

Fix up converted mainboards that still used early_mtrr_init()

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-08-01 17:22:17 +00:00 committed by Stefan Reinauer
parent f97654833a
commit c9ce895199
4 changed files with 2 additions and 13 deletions
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2
src/cpu/x86/mtrr/earlymtrr.c
View File

@ -62,6 +62,7 @@ static inline void cache_lbmem(int type)
enable_cache();
}
#if !defined(CONFIG_USE_DCACHE_RAM) || (CONFIG_USE_DCACHE_RAM == 0)
/* the fixed and variable MTTRs are power-up with random values,
* clear them to MTRR_TYPE_UNCACHEABLE for safty.
*/
@ -118,6 +119,7 @@ static inline void early_mtrr_init(void)
do_early_mtrr_init(mtrr_msrs);
enable_cache();
}
#endif
static inline int early_mtrr_init_detected(void)
{

5
src/mainboard/bcom/winnetp680/romstage.c
View File

@ -95,11 +95,6 @@ void main(unsigned long bist)
enable_smbus();
smbus_fixup(&ctrl);
if (bist == 0) {
print_debug("doing early_mtrr\n");
early_mtrr_init();
}
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);

5
src/mainboard/via/epia-cn/romstage.c
View File

@ -93,11 +93,6 @@ void main(unsigned long bist)
enable_smbus();
smbus_fixup(&ctrl);
if (bist == 0) {
print_debug("doing early_mtrr\n");
early_mtrr_init();
}
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);

3
src/mainboard/via/pc2500e/romstage.c
View File

@ -67,9 +67,6 @@ void main(unsigned long bist)
enable_smbus();
smbus_fixup(&ctrl);
if (bist == 0)
early_mtrr_init();
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);