arch/x86: Implement RESET_VECTOR_IN_RAM

Add support for devices with the reset vector pointing into DRAM.  This
is a specific implementation that assumes a paradigm of AMD Family 17h
(a.k.a. "Zen").  Until the first ljmpl for protected mode, the core's
state appears to software like other designs, and then the actual
physical addressing becomes recognizable.

These systems cannot implement cache-as-RAM as in more traditional
x86 products.  Therefore instead of reusing CAR names and variables,
a substitute called "earlyram" is introduced.  This change makes
adjustments to CAR-aware files accordingly.

Enable NO_XIP_EARLY_STAGES.  The first stage is already in DRAM, and
running subsequent stages as XIP in the boot device would reduce
performance.

Finally, add a new early_ram.ld linker file.  Because all stages run in
DRAM, they can be linked with their .data and .bss as normal, i.e. they
don't need to rely on storage available only at a fixed location like
CAR systems.  The primary purpose of the early_ram.ld is to provide
consistent locations for PRERAM_CBMEM_CONSOLE, TIMESTAMP regions, etc.
across stages until cbmem is brought online.

BUG=b:147042464
TEST=Build for trembyle, and boot to ramstage.
$ objdump -h cbfs/fallback/bootblock.debug
Idx ,Name          ,Size      ,VMA       ,LMA       ,File off  Algn
  0 ,.text         ,000074d0  ,08076000  ,08076000  ,00001000  2**12
  1 ,.data         ,00000038  ,0807d4d0  ,0807d4d0  ,000084d0  2**2
  2 ,.bss          ,00000048  ,0807d508  ,0807d508  ,00008508  2**2
  3 ,.stack        ,00000800  ,0807daf0  ,0807daf0  ,00000000  2**0
  4 ,.persistent   ,00001cfa  ,0807e2f0  ,0807e2f0  ,00000000  2**0
  5 ,.reset        ,00000010  ,0807fff0  ,0807fff0  ,0000aff0  2**0
  6 ,.debug_info   ,0002659c  ,00000000  ,00000000  ,0000b000  2**0
  7 ,.debug_abbrev ,000074a2  ,00000000  ,00000000  ,0003159c  2**0
  8 ,.debug_aranges,00000dd0  ,00000000  ,00000000  ,00038a40  2**3
  9 ,.debug_line   ,0000ad65  ,00000000  ,00000000  ,00039810  2**0
 10 ,.debug_str    ,00009655  ,00000000  ,00000000  ,00044575  2**0
 11 ,.debug_loc    ,0000b7ce  ,00000000  ,00000000  ,0004dbca  2**0
 12 ,.debug_ranges ,000029c0  ,00000000  ,00000000  ,00059398  2**3

Change-Id: I9c084ff6fdcf7e9154436f038705e8679daea780
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35035
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/arch/x86/Kconfig

@@ -89,9 +89,10 @@ config X86_RESET_VECTOR
 config RESET_VECTOR_IN_RAM
 	bool
 	depends on ARCH_X86
+	select NO_XIP_EARLY_STAGES
 	help
-	  Select this option if the x86 soc implements custom code to handle the
+	  Select this option if the x86 processor's reset vector is in
-	  reset vector in RAM instead of the traditional 0xfffffff0 location.
+	  preinitialized DRAM instead of the traditional 0xfffffff0 location.
 
 # Aligns 16bit entry code in bootblock so that hyper-threading CPUs
 # can boot AP CPUs to enable their shared caches.
@@ -206,6 +207,7 @@ config VERSTAGE_ADDR
 config POSTCAR_STAGE
 	def_bool y
 	depends on ARCH_X86
+	depends on !RESET_VECTOR_IN_RAM
 
 config VERSTAGE_DEBUG_SPINLOOP
 	bool

src/arch/x86/assembly_entry.S

@@ -9,6 +9,13 @@
  * continue with C code execution one needs to set stack pointer and
  * clear .bss variables that are stage specific.
  */
+
+#if CONFIG(RESET_VECTOR_IN_RAM)
+	#define _STACK_TOP _eearlyram_stack
+#else
+	#define _STACK_TOP _ecar_stack
+#endif
+
 .section ".text._start", "ax", @progbits
 .global _start
 _start:
@@ -16,8 +23,8 @@ _start:
 	/* Migrate GDT to this text segment */
 	call	gdt_init
 
-	/* reset stack pointer to CAR stack */
+	/* reset stack pointer to CAR/EARLYRAM stack */
-	mov	$_ecar_stack, %esp
+	mov	$_STACK_TOP, %esp
 
 	/* clear .bss section as it is not shared */
 	cld

src/arch/x86/early_ram.ld

@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+/* This file is included inside a SECTIONS block */
+
+_STACK_SIZE = CONFIG_EARLYRAM_BSP_STACK_SIZE;
+_ = ASSERT(_STACK_SIZE > 0x0, "EARLYRAM_BSP_STACK_SIZE is not configured");
+
+_CONSOLE_SIZE = CONFIG_PRERAM_CBMEM_CONSOLE_SIZE;
+_ = ASSERT(_CONSOLE_SIZE > 0x0, "PRERAM_CBMEM_CONSOLE_SIZE is not configured");
+
+_TIMESTAMPS_SIZE = 0x200;
+#if !CONFIG(NO_FMAP_CACHE)
+_FMAP_SIZE = FMAP_SIZE;
+#else
+_FMAP_SIZE = 0;
+#endif
+
+/*
+ * The PRERAM_CBMEM_CONSOLE, TIMESTAMP, and FMAP_CACHE regions are shared
+ * between the pre-ram stages (bootblock, romstage, etc). We need to assign a
+ * fixed size and consistent link address so they can be shared between stages.
+ *
+ * The stack area is not shared between stages, but is defined here for
+ * convenience.
+ */
+. = CONFIG_X86_RESET_VECTOR - ARCH_STACK_ALIGN_SIZE - _STACK_SIZE - _CONSOLE_SIZE - _TIMESTAMPS_SIZE - _FMAP_SIZE;
+
+_ = ASSERT(. > _eprogram, "Not enough room for .earlyram.data. Try increasing C_ENV_BOOTBLOCK_SIZE, or decreasing either EARLYRAM_BSP_STACK_SIZE or PRERAM_CBMEM_CONSOLE_SIZE.");
+
+.stack ALIGN(ARCH_STACK_ALIGN_SIZE) (NOLOAD) : {
+	EARLYRAM_STACK(., _STACK_SIZE)
+}
+
+.persistent ALIGN(ARCH_POINTER_ALIGN_SIZE) (NOLOAD) : {
+	PRERAM_CBMEM_CONSOLE(., _CONSOLE_SIZE)
+	TIMESTAMP(., _TIMESTAMPS_SIZE)
+	#if !CONFIG(NO_FMAP_CACHE)
+		FMAP_CACHE(., FMAP_SIZE)
+	#endif
+}
+
+_ = ASSERT(. <= CONFIG_X86_RESET_VECTOR, "Earlyram data regions don't fit below the reset vector!");

src/arch/x86/include/arch/memlayout.h

@@ -8,4 +8,7 @@
 # error "CONFIG_RAMTOP not configured"
 #endif
 
+/* Intel386 psABI requires a 16 byte aligned stack. */
+#define ARCH_STACK_ALIGN_SIZE 16
+
 #endif /* __ARCH_MEMLAYOUT_H */

src/arch/x86/memlayout.ld

@@ -9,7 +9,7 @@
 #if ENV_CACHE_AS_RAM
 #define EARLY_MEMLAYOUT	"car.ld"
 #else
-#error "Early DRAM environment for x86 is work-in-progress. */
+#define EARLY_MEMLAYOUT	"early_ram.ld"
 #endif
 #endif
 
@@ -53,7 +53,9 @@ SECTIONS
 /* Bootblock specific scripts which provide more SECTION directives. */
 #include <cpu/x86/16bit/entry16.ld>
 #include <cpu/x86/16bit/reset16.ld>
+#if !CONFIG(RESET_VECTOR_IN_RAM)
 #include <arch/x86/id.ld>
+#endif
 #if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
 #include <cpu/intel/fit/fit.ld>
 #endif

src/cpu/Kconfig

@@ -15,6 +15,10 @@ config DCACHE_RAM_SIZE
 config DCACHE_BSP_STACK_SIZE
 	hex
 
+config EARLYRAM_BSP_STACK_SIZE
+	depends on RESET_VECTOR_IN_RAM
+	hex
+
 config SMP
 	bool
 	default y if MAX_CPUS != 1

src/include/memlayout.h

@@ -58,6 +58,9 @@
 #define PRERAM_CBMEM_CONSOLE(addr, size) \
 	REGION(preram_cbmem_console, addr, size, 4)
 
+#define EARLYRAM_STACK(addr, size) \
+	REGION(earlyram_stack, addr, size, ARCH_STACK_ALIGN_SIZE)
+
 /* Use either CBFS_CACHE (unified) or both (PRERAM|POSTRAM)_CBFS_CACHE */
 #define CBFS_CACHE(addr, size) \
 	REGION(cbfs_cache, addr, size, 4) \