AMD fam10: Remove HAVE_ACPI_RESUME support

Change-Id: I62bbba8cfe515b3cae413582ff8d062a20e6741b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/15474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2016-06-27 19:45:19 +03:00 committed by Patrick Georgi
parent 5e59a82c27
commit cb3e16f287
6 changed files with 4 additions and 79 deletions

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@ -116,23 +116,6 @@ static int backup_create_or_update(struct resume_backup *backup_mem,
return 0; return 0;
} }
void *acpi_backup_container(uintptr_t base, size_t size)
{
struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME);
if (!backup_mem)
return NULL;
if (!IS_ALIGNED(base, BACKUP_PAGE_SZ) || !IS_ALIGNED(size,
BACKUP_PAGE_SZ))
return NULL;
if (backup_create_or_update(backup_mem, base, size) < 0)
return NULL;
backup_mem->valid = 1;
return (void *)(uintptr_t)backup_mem->cbmem;
}
void backup_ramstage_section(uintptr_t base, size_t size) void backup_ramstage_section(uintptr_t base, size_t size)
{ {
struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME);

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@ -976,13 +976,6 @@ static inline int acpi_s3_resume_allowed(void)
return CONFIG(HAVE_ACPI_RESUME); return CONFIG(HAVE_ACPI_RESUME);
} }
/* Return address in reserved memory where to backup low memory
* while platform resumes from S3 suspend. Caller is responsible of
* making a complete copy of the region base..base+size, with
* parameteres base and size that meet page alignment requirement.
*/
void *acpi_backup_container(uintptr_t base, size_t size);
#if CONFIG(HAVE_ACPI_RESUME) #if CONFIG(HAVE_ACPI_RESUME)
#ifdef __PRE_RAM__ #ifdef __PRE_RAM__

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@ -27,6 +27,7 @@
#include <cpu/amd/car.h> #include <cpu/amd/car.h>
#include <cpu/amd/msr.h> #include <cpu/amd/msr.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <program_loading.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include "cpu/amd/car/disable_cache_as_ram.c" #include "cpu/amd/car/disable_cache_as_ram.c"
@ -44,12 +45,6 @@
#define print_car_debug(format, arg...) #define print_car_debug(format, arg...)
#endif #endif
static size_t backup_size(void)
{
size_t car_size = car_data_size();
return ALIGN_UP(car_size + 1024, 1024);
}
static void memcpy_(void *d, const void *s, size_t len) static void memcpy_(void *d, const void *s, size_t len)
{ {
print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...", print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...",
@ -58,13 +53,6 @@ static void memcpy_(void *d, const void *s, size_t len)
memcpy(d, s, len); memcpy(d, s, len);
} }
static void memset_(void *d, int val, size_t len)
{
print_car_debug(" Fill [%08x-%08x] ...",
(uint32_t) d, (uint32_t) (d + len - 1));
memset(d, val, len);
}
static int memcmp_(void *d, const void *s, size_t len) static int memcmp_(void *d, const void *s, size_t len)
{ {
print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ...", print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ...",
@ -73,41 +61,6 @@ static int memcmp_(void *d, const void *s, size_t len)
return memcmp(d, s, len); return memcmp(d, s, len);
} }
static void prepare_romstage_ramstack(int s3resume)
{
size_t backup_top = backup_size();
print_car_debug("Prepare CAR migration and stack regions...");
if (s3resume) {
void *resume_backup_memory =
acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
if (resume_backup_memory)
memcpy_(resume_backup_memory
+ HIGH_MEMORY_SAVE - backup_top,
(void *)(CONFIG_RAMTOP - backup_top),
backup_top);
}
memset_((void *)(CONFIG_RAMTOP - backup_top), 0, backup_top);
print_car_debug(" Done\n");
}
static void prepare_ramstage_region(int s3resume)
{
size_t backup_top = backup_size();
print_car_debug("Prepare ramstage memory region...");
if (s3resume) {
void *resume_backup_memory =
acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
if (resume_backup_memory)
memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE,
HIGH_MEMORY_SAVE - backup_top);
}
print_car_debug(" Done\n");
}
/* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33
* and RevGuide for Fam12h, Pub#44739 Rev 3.10 * and RevGuide for Fam12h, Pub#44739 Rev 3.10
*/ */
@ -137,9 +90,10 @@ asmlinkage void *post_cache_as_ram(void)
if ((*lower_stack_boundary) != 0xdeadbeef) if ((*lower_stack_boundary) != 0xdeadbeef)
printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n");
s3resume = acpi_is_wakeup_s3();
prepare_romstage_ramstack(s3resume); /* ACPI S3 is not supported without RELOCATABLE_RAMSTAGE and
* this will always return 0. */
s3resume = acpi_is_wakeup_s3();
romstage_handoff_init(s3resume); romstage_handoff_init(s3resume);
@ -177,8 +131,6 @@ asmlinkage void cache_as_ram_new_stack(void)
set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache(); enable_cache();
prepare_ramstage_region(acpi_is_wakeup_s3());
set_sysinfo_in_ram(1); // So other core0 could start to train mem set_sysinfo_in_ram(1); // So other core0 could start to train mem
/*copy and execute ramstage */ /*copy and execute ramstage */

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@ -10,7 +10,6 @@ config CPU_AMD_MODEL_10XXX
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_MICROCODE_MULTIPLE_FILES select CPU_MICROCODE_MULTIPLE_FILES
select CAR_GLOBAL_MIGRATION select CAR_GLOBAL_MIGRATION
select ACPI_HUGE_LOWMEM_BACKUP
if CPU_AMD_MODEL_10XXX if CPU_AMD_MODEL_10XXX

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@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_2048 select BOARD_ROMSIZE_KB_2048
select ENABLE_APIC_EXT_ID select ENABLE_APIC_EXT_ID
select SPI_FLASH select SPI_FLASH
select HAVE_ACPI_RESUME
select DRIVERS_I2C_W83795 select DRIVERS_I2C_W83795
select DRIVERS_ASPEED_AST2050 select DRIVERS_ASPEED_AST2050
select MAINBOARD_FORCE_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT

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@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS
select ENABLE_APIC_EXT_ID select ENABLE_APIC_EXT_ID
select SPI_FLASH select SPI_FLASH
select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_LPC_TPM
select HAVE_ACPI_RESUME
select DRIVERS_I2C_W83795 select DRIVERS_I2C_W83795
select DRIVERS_ASPEED_AST2050 select DRIVERS_ASPEED_AST2050
select MAINBOARD_FORCE_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT