soc/intel/skylake: Make use of Intel common Graphics block
TEST=Build and boot soraka/eve. Change-Id: I416226d0374700cea6eea602f839c3d17f1f39a6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -61,6 +61,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_GPIO
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select SOC_INTEL_COMMON_BLOCK_GPIO
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select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
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select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
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select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
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select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
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select SOC_INTEL_COMMON_BLOCK_GRAPHICS
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select SOC_INTEL_COMMON_BLOCK_GSPI
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select SOC_INTEL_COMMON_BLOCK_GSPI
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select SOC_INTEL_COMMON_BLOCK_ITSS
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select SOC_INTEL_COMMON_BLOCK_ITSS
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select SOC_INTEL_COMMON_BLOCK_I2C
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select SOC_INTEL_COMMON_BLOCK_I2C
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@ -52,7 +52,7 @@ ramstage-y += finalize.c
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ramstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += gspi.c
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ramstage-y += gspi.c
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ramstage-y += i2c.c
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ramstage-y += i2c.c
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ramstage-y += igd.c
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ramstage-y += graphics.c
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ramstage-y += irq.c
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ramstage-y += irq.c
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ramstage-y += lockdown.c
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ramstage-y += lockdown.c
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ramstage-y += lpc.c
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ramstage-y += lpc.c
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@ -2,7 +2,7 @@
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* This file is part of the coreboot project.
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* This file is part of the coreboot project.
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*
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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* Copyright (C) 2015-2017 Intel Corporation.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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@ -14,87 +14,46 @@
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <bootmode.h>
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#include <chip.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <drivers/intel/gma/i915_reg.h>
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#include <drivers/intel/gma/i915_reg.h>
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#include <intelblocks/graphics.h>
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#include <soc/intel/common/opregion.h>
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#include <soc/intel/common/opregion.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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#include <soc/pm.h>
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#include <soc/ramstage.h>
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#include <soc/ramstage.h>
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#include <soc/systemagent.h>
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#include <stdlib.h>
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#include <string.h>
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#include <security/vboot/vbnv.h>
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uintptr_t fsp_soc_get_igd_bar(void)
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uintptr_t fsp_soc_get_igd_bar(void)
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{
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{
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device_t dev = SA_DEV_IGD;
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return graphics_get_memory_base();
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/* Check if IGD PCI device is disabled */
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if (!dev->enabled)
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return 0;
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return find_resource(dev, PCI_BASE_ADDRESS_2)->base;
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}
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}
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u32 map_oprom_vendev(u32 vendev)
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void graphics_soc_init(struct device *dev)
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{
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return SA_IGD_OPROM_VENDEV;
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}
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static struct resource *gtt_res = NULL;
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static unsigned long gtt_read(unsigned long reg)
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{
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u32 val;
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val = read32((void *)(unsigned int)(gtt_res->base + reg));
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return val;
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}
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static void gtt_write(unsigned long reg, unsigned long data)
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{
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write32((void *)(unsigned int)(gtt_res->base + reg), data);
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}
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static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
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{
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u32 val = gtt_read(reg);
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val &= andmask;
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val |= ormask;
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gtt_write(reg, val);
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}
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static void igd_init(struct device *dev)
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{
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{
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u32 ddi_buf_ctl;
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u32 ddi_buf_ctl;
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gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (!gtt_res || !gtt_res->base)
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return;
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/*
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/*
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* Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
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* Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
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* This will allow the kernel to use 4-lane eDP links properly
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* This will allow the kernel to use 4-lane eDP links properly
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* if the VBIOS or GOP driver does not execute.
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* if the VBIOS or GOP driver does not execute.
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*/
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*/
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ddi_buf_ctl = gtt_read(DDI_BUF_CTL_A);
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ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
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if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
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if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) {
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ddi_buf_ctl |= DDI_A_4_LANES;
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ddi_buf_ctl |= DDI_A_4_LANES;
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gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
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graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
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}
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}
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/*
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* GFX PEIM module inside FSP binary is taking care of graphics
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* initialization based on INTEL_GMA_ADD_VBT_DATA_FILE Kconfig
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* option and input VBT file. Hence no need to load/execute legacy VGA
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* OpROM in order to initialize GFX.
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*
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* In case of non-FSP solution, SoC need to select VGA_ROM_RUN
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* Kconfig to perform GFX initialization through VGA OpRom.
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*/
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if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE))
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if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE))
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return;
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return;
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/* IGD needs to be Bus Master */
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/* IGD needs to Bus Master */
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u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
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u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
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reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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pci_write_config32(dev, PCI_COMMAND, reg32);
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@ -104,7 +63,7 @@ static void igd_init(struct device *dev)
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}
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}
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/* Initialize IGD OpRegion, called from ACPI code */
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/* Initialize IGD OpRegion, called from ACPI code */
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static int update_igd_opregion(igd_opregion_t *opregion)
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static void update_igd_opregion(igd_opregion_t *opregion)
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{
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{
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u16 reg16;
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u16 reg16;
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@ -131,12 +90,10 @@ static int update_igd_opregion(igd_opregion_t *opregion)
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reg16 &= ~GSSCIE;
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reg16 &= ~GSSCIE;
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reg16 |= SMISCISEL;
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reg16 |= SMISCISEL;
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pci_write_config16(SA_DEV_IGD, SWSCI, reg16);
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pci_write_config16(SA_DEV_IGD, SWSCI, reg16);
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return 0;
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}
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}
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static unsigned long write_acpi_igd_opregion(device_t device,
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uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
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unsigned long current, struct acpi_rsdp *rsdp)
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uintptr_t current, struct acpi_rsdp *rsdp)
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{
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{
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igd_opregion_t *opregion;
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igd_opregion_t *opregion;
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@ -161,33 +118,3 @@ static unsigned long write_acpi_igd_opregion(device_t device,
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printk(BIOS_DEBUG, "current = %lx\n", current);
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printk(BIOS_DEBUG, "current = %lx\n", current);
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return current;
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return current;
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}
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}
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static struct device_operations igd_ops = {
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.read_resources = &pci_dev_read_resources,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.init = &igd_init,
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.ops_pci = &soc_pci_ops,
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.write_acpi_tables = write_acpi_igd_opregion,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM,
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PCI_DEVICE_ID_INTEL_SKL_GT2_SULXM,
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PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM,
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PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM,
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PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM,
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PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM,
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PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM,
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PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM,
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PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM,
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PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR,
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PCI_DEVICE_ID_INTEL_KBL_GT2_SHALM,
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0,
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};
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static const struct pci_driver igd_driver __pci_driver = {
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.ops = &igd_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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