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cpu/intel/common: correct MSR for the Nominal Performance in CPPC 

The "Nominal Performance" is not the same as the "Guaranteed
Performance", but is defined as the performance a processor can deliver
continously under ideal environmental conditions.

According to edk2, this is the "Maximum Non-Turbo Ratio", which needs to
be read from MSR_PLATFORM_INFO instead of IA32_HWP_CAPABILITIES.

Correct the entry in the CPPC package.

Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled
version

Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46464
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2020-10-15 16:11:19 +02:00
parent 1b940d17a8
commit cbd4ee73d7
2 changed files with 11 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/cpu/intel/common/common_init.c
View File

@ -130,13 +130,6 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
*/
config->regs[CPPC_HIGHEST_PERF] = msr;
/*
* Nominal Performance -> Guaranteed Performance:
* ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)},
*/
msr.bit_offset = 8;
config->regs[CPPC_NOMINAL_PERF] = msr;
/*
* Lowest Nonlinear Performance -> Most Efficient Performance:
* ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)},
@ -158,6 +151,15 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
msr.bit_offset = 8;
config->regs[CPPC_GUARANTEED_PERF] = msr;
msr.addrl = MSR_PLATFORM_INFO;
/*
* Nominal Performance -> Maximum Non-Turbo Ratio:
* ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0xce, 0x04,)},
*/
msr.bit_offset = 8;
config->regs[CPPC_NOMINAL_PERF] = msr;
msr.addrl = IA32_HWP_REQUEST;
/*

2
src/include/cpu/intel/msr.h
View File

@ -12,4 +12,6 @@
#define MSR_PIC_MSG_CONTROL 0x2e
#define TPR_UPDATES_DISABLE (1 << 10)
#define MSR_PLATFORM_INFO 0xce
#endif /* CPU_INTEL_MSR_H */