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soc/amd: rename ACPI_CPU_CONTROL to ACPI_CSTATE_CONTROL for non-CAR CPUs 

The legacy ACPI CPU control registers in IO space where the first 4 IO
locations control the CPU throttling value don't exist any more on the
Zen-based CPUs. Instead this IO address is written to MSR_CSTATE_ADDRESS
in set_cstate_io_addr which will cause accesses from the 8 IO addresses
beginning with ACPI_CSTATE_CONTROL to be trapped in the CPU core. Reads
from those IO addresses will cause the CPU to enter low C states.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2c34e201cc0add1026edd7a97c70aa57f057782b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Felix Held 2023-03-03 22:37:34 +01:00
parent c8755141c0
commit cbe55a1728
6 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/amd/cezanne/include/soc/iomap.h
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@ -42,7 +42,7 @@
#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02)
#define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04)
#define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08)
#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10)
#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10)
#define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20)
#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00)
#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04)

2
src/soc/amd/common/block/cpu/noncar/cpu.c
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@ -24,6 +24,6 @@ void set_cstate_io_addr(void)
msr_t cst_addr;
cst_addr.hi = 0;
cst_addr.lo = ACPI_CPU_CONTROL;
cst_addr.lo = ACPI_CSTATE_CONTROL;
wrmsr(MSR_CSTATE_ADDRESS, cst_addr);
}

2
src/soc/amd/glinda/include/soc/iomap.h
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@ -50,7 +50,7 @@
#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02)
#define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04)
#define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08)
#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10)
#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10)
#define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20)
#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00)
#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04)

2
src/soc/amd/mendocino/include/soc/iomap.h
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@ -48,7 +48,7 @@
#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02)
#define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04)
#define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08)
#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10)
#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10)
#define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20)
#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00)
#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04)

2
src/soc/amd/phoenix/include/soc/iomap.h
View File

@ -48,7 +48,7 @@
#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02)
#define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04)
#define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08)
#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10)
#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10)
#define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20)
#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00)
#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04)

4
src/soc/amd/picasso/include/soc/iomap.h
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@ -69,8 +69,8 @@
#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */
#define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) /* 2 bytes */
#define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) /* 4 bytes */
#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) /* 8 bytes */
/* doc says 0x14 for GPE0_BLK but 8 bytes from ACPI_CPU_CONTROL on are trapped in CPU core */
#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) /* 8 bytes */
/* doc says 0x14 for GPE0_BLK but 8 bytes from ACPI_CSTATE_CONTROL on are trapped in CPU core */
#define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */
#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */
#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */