Define global uma_memory variables

Use of the uma_memory_base and _size variables is very scattered.
Implementation of setup_uma_memory() will appear in each northbridge.

It should be possible to do this setup entirely in northbridge
code and get rid of the globals in a follow-up.

Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

src/cpu/amd/mtrr/amd_mtrr.c

@@ -6,10 +6,6 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_size;
-#endif
-
 static unsigned long resk(uint64_t value)
 {
 	unsigned long resultk;

src/cpu/x86/mtrr/mtrr.c

@@ -40,10 +40,6 @@
 #include <arch/cpu.h>
 #include <arch/acpi.h>
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static unsigned int mtrr_msr[] = {
 	MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
 	MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,

src/devices/device.c

@@ -54,6 +54,11 @@ struct resource *free_resources = NULL;
 
 DECLARE_SPIN_LOCK(dev_lock)
 
+
+/* IGD UMA memory */
+uint64_t uma_memory_base = 0;
+uint64_t uma_memory_size = 0;
+
 /**
  * Allocate a new device structure.
  *

src/include/device/device.h

@@ -110,6 +110,11 @@ extern struct device	*all_devices;	/* list of all devices */
 extern struct resource	*free_resources;
 extern struct bus	*free_links;
 
+/* IGD UMA memory */
+void setup_uma_memory(void);
+extern uint64_t uma_memory_base;
+extern uint64_t uma_memory_size;
+
 /* Generic device interface functions */
 device_t alloc_dev(struct bus *parent, struct device_path *path);
 void dev_enumerate(void);

src/mainboard/advansus/a785e-i/mainboard.c

@@ -28,7 +28,6 @@
 #include "SBPLATFORM.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
 
 u8 is_dev3_present(void);
 void set_pcie_dereset(void);

src/mainboard/amd/bimini_fam10/mainboard.c

@@ -28,7 +28,6 @@
 #include <southbridge/amd/sb800/sb800.h>
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
 
 u8 is_dev3_present(void);
 void set_pcie_dereset(void);

src/mainboard/amd/dbm690t/mainboard.c

@@ -42,7 +42,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /********************************************************
 * dbm690t uses a BCM5789 as on-board NIC.

src/mainboard/amd/dinar/mainboard.c

@@ -67,7 +67,6 @@ void set_pcie_dereset(void *nbconfig)
 	}
 }
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
  * enable the dedicated function in dinar board.

src/mainboard/amd/inagua/mainboard.c

@@ -71,7 +71,6 @@ void set_pcie_dereset(void)
 	RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG50, AccWidthUint8, ~(0xFF), 0x48);
 }
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
  * enable the dedicated function in INAGUA    board.

src/mainboard/amd/mahogany/mainboard.c

@@ -29,8 +29,6 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);

src/mainboard/amd/mahogany_fam10/mainboard.c

@@ -29,8 +29,6 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);

src/mainboard/amd/persimmon/mainboard.c

@@ -50,7 +50,6 @@ void set_pcie_dereset(void)
 {
 }
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
 * enable the dedicated function in persimmon board.

src/mainboard/amd/pistachio/mainboard.c

@@ -39,7 +39,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
 #define ADT7475_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /********************************************************
 * pistachio uses a BCM5787 as on-board NIC.

src/mainboard/amd/south_station/mainboard.c

@@ -28,7 +28,6 @@
 #include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
 
 void set_pcie_reset(void);
 void set_pcie_dereset(void);

src/mainboard/amd/tilapia_fam10/mainboard.c

@@ -39,8 +39,6 @@
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);

src/mainboard/amd/torpedo/mainboard.c

@@ -50,7 +50,6 @@ void set_pcie_dereset(void)
 {
 }
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
 * enable the dedicated function in torpedo board.

src/mainboard/amd/union_station/mainboard.c

@@ -47,7 +47,6 @@ void set_pcie_dereset(void)
 {
 }
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
 * enable the dedicated function in unionstation board.

src/mainboard/asrock/939a785gmh/mainboard.c

@@ -29,8 +29,6 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);

src/mainboard/asrock/e350m1/mainboard.c

@@ -46,7 +46,6 @@ void set_pcie_dereset(void)
 {
 }
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
 * enable the dedicated function in e350m1 board.

src/mainboard/asus/m2v-mx_se/mainboard.c

@@ -24,10 +24,6 @@
 #include <southbridge/via/k8t890/k8t890.h>
 #include "chip.h"
 
-#if CONFIG_GFXUMA
-uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 int add_mainboard_resources(struct lb_memory *mem)
 {
 #if CONFIG_GFXUMA

src/mainboard/asus/m4a78-em/mainboard.c

@@ -29,8 +29,6 @@
 #include "chip.h"
 
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);

src/mainboard/asus/m4a785-m/mainboard.c

@@ -38,8 +38,6 @@
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);

src/mainboard/asus/m5a88-v/mainboard.c

@@ -28,7 +28,6 @@
 #include "SBPLATFORM.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
 
 u8 is_dev3_present(void);
 void set_pcie_dereset(void);

src/mainboard/avalue/eax-785e/mainboard.c

@@ -28,7 +28,6 @@
 #include "SBPLATFORM.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
 
 u8 is_dev3_present(void);
 void set_pcie_dereset(void);

src/mainboard/gigabyte/ma785gm/mainboard.c

@@ -29,8 +29,6 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 int is_dev3_present(void);

src/mainboard/gigabyte/ma785gmt/mainboard.c

@@ -39,8 +39,6 @@
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 int is_dev3_present(void);

src/mainboard/gigabyte/ma78gm/mainboard.c

@@ -30,8 +30,6 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);

src/mainboard/iei/kino-780am2-fam10/mainboard.c

@@ -29,8 +29,6 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);

src/mainboard/jetway/pa78vm5/mainboard.c

@@ -30,8 +30,6 @@
 #include "southbridge/amd/sb700/smbus.h"
 #include "chip.h"
 
-uint64_t uma_memory_base, uma_memory_size;
-
 void set_pcie_dereset(void);
 void set_pcie_reset(void);
 u8 is_dev3_present(void);

src/mainboard/kontron/kt690/mainboard.c

@@ -42,7 +42,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /********************************************************
 * dbm690t uses a BCM5789 as on-board NIC.

src/mainboard/siemens/sitemp_g1p1/mainboard.c

@@ -162,7 +162,6 @@
 extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
 extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
 
-uint64_t uma_memory_base, uma_memory_size;
 static u32 smbus_io_base = SMBUS_IO_BASE;
 static u32 adt7475_address = ADT7475_ADDRESS;
 

src/mainboard/technexion/tim5690/mainboard.c

@@ -83,7 +83,6 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
 
 /* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
    LDN the register belongs to, before you can access the register. */

src/mainboard/technexion/tim8690/mainboard.c

@@ -42,7 +42,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
 #define ADT7461_write_byte(address, val) \
 	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
 
-uint64_t uma_memory_base, uma_memory_size;
 
 
 

src/northbridge/amd/agesa/family10/northbridge.c

@@ -908,10 +908,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 }
 #endif
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void amdfam10_domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM

src/northbridge/amd/agesa/family12/northbridge.c

@@ -338,10 +338,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 }
 #endif
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void read_resources(device_t dev)
 {
     u32 nodeid;

src/northbridge/amd/agesa/family14/northbridge.c

@@ -326,10 +326,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 }
 #endif
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void read_resources(device_t dev)
 {
 	u32 nodeid;

src/northbridge/amd/agesa/family15/northbridge.c

@@ -626,10 +626,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 }
 #endif
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM

src/northbridge/amd/agesa/family15tn/northbridge.c

@@ -613,10 +613,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 }
 #endif
 
-#if CONFIG_GFXUMA == 1
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM == 1

src/northbridge/amd/amdfam10/northbridge.c

@@ -847,10 +847,6 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id)
 #include <cbmem.h>
 #endif
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void amdfam10_domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM

src/northbridge/amd/amdk8/northbridge.c

@@ -822,10 +822,6 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id)
 #include <cbmem.h>
 #endif
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void amdk8_domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM

src/northbridge/intel/i82810/northbridge.c

@@ -62,9 +62,6 @@ static const struct pci_driver i810e_northbridge_driver __pci_driver = {
 	.device = 0x7124,
 };
 
-/* IGD UMA memory */
-uint64_t uma_memory_base=0, uma_memory_size=0;
-
 int add_northbridge_resources(struct lb_memory *mem)
 {
 	printk(BIOS_DEBUG, "Adding IGD UMA memory area\n");

src/northbridge/intel/i82830/northbridge.c

@@ -52,9 +52,6 @@ static const struct pci_driver northbridge_driver __pci_driver = {
 	.device = 0x3575,
 };
 
-/* IGD memory */
-uint64_t uma_memory_base=0, uma_memory_size=0;
-
 int add_northbridge_resources(struct lb_memory *mem)
 {
 	printk(BIOS_DEBUG, "Adding IGD UMA memory area\n");

src/northbridge/intel/i945/northbridge.c

@@ -68,9 +68,6 @@ static int get_pcie_bar(u32 *base, u32 *len)
 	return 0;
 }
 
-/* IDG memory */
-uint64_t uma_memory_base=0, uma_memory_size=0;
-
 static void add_fixed_resources(struct device *dev, int index)
 {
 	struct resource *resource;

src/northbridge/intel/sandybridge/northbridge.c

@@ -118,9 +118,6 @@ static int get_pcie_bar(u32 *base, u32 *len)
 	return 0;
 }
 
-/* IDG memory */
-uint64_t uma_memory_base=0, uma_memory_size=0;
-
 static void add_fixed_resources(struct device *dev, int index)
 {
 	struct resource *resource;

src/northbridge/intel/sch/northbridge.c

@@ -73,9 +73,6 @@ static int get_pcie_bar(u32 *base, u32 *len)
 	return 0;
 }
 
-/* IDG memory */
-u64 uma_memory_base = 0, uma_memory_size = 0;
-
 static void add_fixed_resources(struct device *dev, int index)
 {
 	struct resource *resource;

src/southbridge/amd/rs690/cmn.c

@@ -315,8 +315,6 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 */
 void rs690_set_tom(device_t nb_dev)
 {
-	extern uint64_t uma_memory_base;
-
 	/* set TOM */
 	pci_write_config32(nb_dev, 0x90, uma_memory_base);
 	nbmc_write_index(nb_dev, 0x1e, uma_memory_base);

src/southbridge/amd/rs780/cmn.c

@@ -356,8 +356,6 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 */
 void rs780_set_tom(device_t nb_dev)
 {
-	extern uint64_t uma_memory_base;
-
 	/* set TOM */
 	pci_write_config32(nb_dev, 0x90, uma_memory_base);
 	//nbmc_write_index(nb_dev, 0x1e, uma_memory_base);

src/southbridge/amd/rs780/gfx.c

@@ -43,8 +43,6 @@ extern int is_dev3_present(void);
 void set_pcie_reset(void);
 void set_pcie_dereset(void);
 
-extern uint64_t uma_memory_base, uma_memory_size;
-
 /* Trust the original resource allocation. Don't do it again. */
 #undef DONT_TRUST_RESOURCE_ALLOCATION
 //#define DONT_TRUST_RESOURCE_ALLOCATION

src/southbridge/amd/rs780/rs780.c

@@ -221,7 +221,6 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 	/* Program Straps. */
 	romstrap2 = 1 << 26; // enables audio function
 #if CONFIG_GFXUMA
-	extern uint64_t uma_memory_size;
 	// bits 7-9: aperture size
 	// 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g
 	if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7;

src/southbridge/via/k8t890/dram.c

@@ -71,10 +71,6 @@ static void dram_enable(struct device *dev)
 
 }
 
-#if CONFIG_GFXUMA
-extern uint64_t uma_memory_base, uma_memory_size;
-#endif
-
 static void dram_enable_k8m890(struct device *dev)
 {
 #if CONFIG_GFXUMA