google/kukui: Configure AP_IN_SLEEP_L correctly
This pin should be set to its alternative function SRCLKENA0 instead of GPIO, so that SPM (a power management component of MT8183) can control it. BUG=b:113367227 BRANCH=none TEST=1. Boot. Run 'powerinfo' in EC console and see power state in S0. 2. Run 'powerd_dbus_suspend --wakeup_timeout=10', and then run 'powerinfo' in EC console and see power state in S3. 3. Wait until AP resume. 4. Run 'powerinfo' in EC console and see power state back to S0. Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32120 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
61d365fafd
commit
cc86d8921b
1 changed files with 1 additions and 2 deletions
|
@ -32,8 +32,7 @@ void mainboard_early_init(void)
|
|||
|
||||
setup_chromeos_gpios();
|
||||
|
||||
/* Declare we are in S0 */
|
||||
gpio_output(AP_IN_SLEEP_L, 1);
|
||||
gpio_set_mode(AP_IN_SLEEP_L, PAD_SRCLKENA0_FUNC_SRCLKENA0);
|
||||
|
||||
mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz);
|
||||
gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
|
||||
|
|
Loading…
Reference in a new issue