binaryPI: Fix cache coherency use for AP CPUs
The memory between _car_region_start .. _car_region_end has to be set up as WB in MTRRs for all the cores executing through bootblock, verstage and romstage. Otherwise global variables may fail on AP CPUs. Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n, which previously did not boot at all for some cases. Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/26115 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -1438,6 +1438,13 @@ SetupStack:
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_WRMSR #
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_WRMSR #
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# All cores must see BSP stack region that is also used to
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# communicate global variables before DRAM is up.
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mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250
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_RDMSR
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or $0x1e000000, %eax
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_WRMSR
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# Enable MTRR defaults as UC type
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# Enable MTRR defaults as UC type
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mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
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mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
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_RDMSR # Read-modify-write the MSR
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_RDMSR # Read-modify-write the MSR
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@ -1179,6 +1179,13 @@ w64k_here:
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_WRMSR #
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_WRMSR #
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# All cores must see BSP stack region that is also used to
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# communicate global variables before DRAM is up.
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mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250
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_RDMSR
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or $0x1e000000, %eax
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_WRMSR
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# Enable MTRR defaults as UC type
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# Enable MTRR defaults as UC type
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mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
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mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
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_RDMSR # Read-modify-write the MSR
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_RDMSR # Read-modify-write the MSR
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@ -1158,6 +1158,13 @@ w64k_here:
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0:
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0:
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_WRMSR #
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_WRMSR #
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# All cores must see BSP stack region that is also used to
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# communicate global variables before DRAM is up.
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mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250
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_RDMSR
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or $0x1e000000, %eax
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_WRMSR
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# Enable MTRR defaults as UC type
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# Enable MTRR defaults as UC type
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mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
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mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
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_RDMSR # Read-modify-write the MSR
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_RDMSR # Read-modify-write the MSR
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@ -1153,6 +1153,13 @@ SetupStack:
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0:
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0:
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_WRMSR #
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_WRMSR #
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# All cores must see BSP stack region that is also used to
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# communicate global variables before DRAM is up.
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mov $AMD_MTRR_FIX64k_00000, %ecx # MSR:0000_0250
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_RDMSR
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or $0x1e000000, %eax
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_WRMSR #
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# Enable MTRR defaults as UC type
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# Enable MTRR defaults as UC type
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mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
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mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
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_RDMSR # Read-modify-write the MSR
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_RDMSR # Read-modify-write the MSR
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