soc/intel/baytrail,denverton_ns: Call setup_lapic()

A custom board with soc/intel/denverton_ns does not respond to
the keyboard and does not boot from the sata/USB disks.
Last post code 0x7b and the last line that is displayed at log
from SeaBIOS is:
   All threads complete.

The issue is gone when adding setup_lapic() call to configure
EXTINT delivery of i8259 originated interrupts for the LAPIC.
Replicate call from other soc/ and make the call for both BSP
and AP CPUs.

Similar change was done for soc/intel/braswell in
commit b4f57bb3ca.

Signed-off-by: Dmitry Ponamorev <dponamorev@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: Iafbfb733d0be546e0e2fba937fd1d262785aa54d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/baytrail/cpu.c

@@ -36,6 +36,9 @@ static void soc_core_init(struct device *cpu)
 {
 	printk(BIOS_DEBUG, "Init BayTrail core.\n");
 
+	/* Enable the local CPU apics */
+	setup_lapic();
+
 	/*
 	 * The turbo disable bit is actually scoped at building block level -- not package.
 	 * For non-BSP cores that are within a building block, enable turbo. The cores within

src/soc/intel/denverton_ns/cpu.c

@@ -3,6 +3,7 @@
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cr.h>
+#include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
@@ -91,6 +92,9 @@ static void denverton_core_init(struct device *cpu)
 	/* Enable Turbo */
 	enable_turbo();
 
+	/* Enable the local CPU apics */
+	setup_lapic();
+
 	/* Enable speed step. Always ON.*/
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= SPEED_STEP_ENABLE_BIT;