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cpu/intel/model_206ax: Remove fake lapic device 

Instead of using a fake lapic device hook up the cpu cluster to chip
cpu/intel/model_206ax.

The lapic device is also not needed as the mp init will allocate it for
the BSP at runtime.

Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans 2021-11-15 20:12:02 +01:00
parent d52bfbb6aa
commit cdb26fd011
12 changed files with 40 additions and 90 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
src/cpu/intel/model_206ax/acpi.c
View File

@ -95,18 +95,9 @@ static int get_logical_cores_per_package(void)
return msr.lo & 0xffff;
}
static void generate_C_state_entries(void)
static void generate_C_state_entries(const struct device *dev)
{
struct device *lapic;
struct cpu_intel_model_206ax_config *conf = NULL;
/* Find the SpeedStep CPU in the device tree using magic APIC ID */
lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
if (!lapic)
return;
conf = lapic->chip_info;
if (!conf)
return;
struct cpu_intel_model_206ax_config *conf = dev->bus->dev->chip_info;
const int acpi_cstates[3] = { conf->acpi_c1, conf->acpi_c2, conf->acpi_c3 };
@ -324,7 +315,7 @@ void generate_cpu_entries(const struct device *device)
cpuID-1, cores_per_package);
/* Generate C-state tables */
generate_C_state_entries();
generate_C_state_entries(device);
/* Generate T-state tables */
generate_T_state_entries(

3
src/cpu/intel/model_206ax/chip.h
View File

@ -1,8 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Magic value used to locate this chip in the device tree */
#define SPEEDSTEP_APIC_MAGIC 0xACAC
/* Keep this in sync with acpi.c */
enum cpu_acpi_level {
CPU_ACPI_DISABLED = 0,

13
src/cpu/intel/model_206ax/model_206ax_init.c
View File

@ -211,18 +211,11 @@ static void configure_c_states(void)
wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
}
static void configure_thermal_target(void)
static void configure_thermal_target(struct device *dev)
{
struct cpu_intel_model_206ax_config *conf;
struct device *lapic;
struct cpu_intel_model_206ax_config *conf = dev->bus->dev->chip_info;
msr_t msr;
/* Find pointer to CPU configuration */
lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
if (!lapic || !lapic->chip_info)
return;
conf = lapic->chip_info;
/* Set TCC activation offset if supported */
msr = rdmsr(MSR_PLATFORM_INFO);
if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
@ -346,7 +339,7 @@ static void model_206ax_init(struct device *cpu)
configure_misc();
/* Thermal throttle activation offset */
configure_thermal_target();
configure_thermal_target(cpu);
set_aesni_lock();

10
src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb
View File

@ -1,10 +1,8 @@
chip northbridge/intel/sandybridge
device cpu_cluster 0 on
chip cpu/intel/model_206ax
register "tcc_offset" = "5" # TCC of 95C
device lapic 0 on end
device lapic 0xacac off end
end
chip cpu/intel/model_206ax
device cpu_cluster 0 on end
register "tcc_offset" = "5" # TCC of 95C
end
device domain 0 on

10
src/mainboard/google/stout/devicetree.cb
View File

@ -19,14 +19,10 @@ chip northbridge/intel/sandybridge
register "max_mem_clock_mhz" = "666"
device cpu_cluster 0 on
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
device lapic 0 on end
device lapic 0xacac off end
chip cpu/intel/model_206ax
device cpu_cluster 0 on end
register "tcc_offset" = "5" # TCC of 95C
end
register "tcc_offset" = "5" # TCC of 95C
end
device domain 0 on

13
src/mainboard/intel/emeraldlake2/devicetree.cb
View File

@ -11,15 +11,12 @@ chip northbridge/intel/sandybridge
# Enable DVI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
device cpu_cluster 0 on
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
device lapic 0 on end
device lapic 0xacac off end
register "acpi_c1" = "CPU_ACPI_C3"
register "acpi_c2" = "CPU_ACPI_C6"
end
chip cpu/intel/model_206ax
device cpu_cluster 0 on end
register "acpi_c1" = "CPU_ACPI_C3"
register "acpi_c2" = "CPU_ACPI_C6"
end
device domain 0 on

12
src/mainboard/kontron/ktqm77/devicetree.cb
View File

@ -2,15 +2,11 @@ chip northbridge/intel/sandybridge
# IGD Displays
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
device cpu_cluster 0 on
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
device lapic 0 on end
device lapic 0xacac off end
chip cpu/intel/model_206ax
device cpu_cluster 0 on end
register "acpi_c2" = "CPU_ACPI_C6"
register "acpi_c3" = "CPU_ACPI_DISABLED"
end
register "acpi_c2" = "CPU_ACPI_C6"
register "acpi_c3" = "CPU_ACPI_DISABLED"
end
device domain 0 on

12
src/mainboard/roda/rv11/variants/rv11/devicetree.cb
View File

@ -17,15 +17,11 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x0000001a"
register "gpu_pch_backlight" = "0x002e0000"
device cpu_cluster 0 on
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
device lapic 0 on end
device lapic 0xacac off end
chip cpu/intel/model_206ax
device cpu_cluster 0 on end
register "acpi_c2" = "CPU_ACPI_C6"
register "acpi_c3" = "CPU_ACPI_DISABLED"
end
register "acpi_c2" = "CPU_ACPI_C6"
register "acpi_c3" = "CPU_ACPI_DISABLED"
end
device domain 0 on

12
src/mainboard/roda/rv11/variants/rw11/devicetree.cb
View File

@ -17,15 +17,11 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x00000ac8"
register "gpu_pch_backlight" = "0x13120000"
device cpu_cluster 0 on
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
device lapic 0 on end
device lapic 0xacac off end
chip cpu/intel/model_206ax
device cpu_cluster 0 on end
register "acpi_c2" = "CPU_ACPI_C6"
register "acpi_c3" = "CPU_ACPI_DISABLED"
end
register "acpi_c2" = "CPU_ACPI_C6"
register "acpi_c3" = "CPU_ACPI_DISABLED"
end
device domain 0 on

12
src/mainboard/samsung/stumpy/devicetree.cb
View File

@ -11,15 +11,11 @@ chip northbridge/intel/sandybridge
register "max_mem_clock_mhz" = "666"
device cpu_cluster 0 on
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
device lapic 0 on end
device lapic 0xacac off end
chip cpu/intel/model_206ax
device cpu_cluster 0 on end
register "acpi_c1" = "CPU_ACPI_C3"
register "acpi_c2" = "CPU_ACPI_C6"
end
register "acpi_c1" = "CPU_ACPI_C3"
register "acpi_c2" = "CPU_ACPI_C6"
end
device domain 0 on

16
src/northbridge/intel/sandybridge/chipset.cb
View File

@ -1,19 +1,13 @@
# SPDX-License-Identifier: GPL-2.0-only
chip northbridge/intel/sandybridge
device cpu_cluster 0 on
ops sandybridge_cpu_bus_ops
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
device lapic 0 on end
device lapic 0xacac off end
chip cpu/intel/model_206ax
device cpu_cluster 0 on ops sandybridge_cpu_bus_ops end
register "acpi_c1" = "CPU_ACPI_C1"
register "acpi_c2" = "CPU_ACPI_C3"
register "acpi_c3" = "CPU_ACPI_C7"
end
register "acpi_c1" = "CPU_ACPI_C1"
register "acpi_c2" = "CPU_ACPI_C3"
register "acpi_c3" = "CPU_ACPI_C7"
end
device domain 0 on
ops sandybridge_pci_domain_ops
end

2
src/northbridge/intel/sandybridge/northbridge.c
View File

@ -387,7 +387,6 @@ static void set_above_4g_pci(const struct device *dev)
static void mc_gen_ssdt(const struct device *dev)
{
generate_cpu_entries(dev);
set_above_4g_pci(dev);
}
@ -416,6 +415,7 @@ struct device_operations sandybridge_cpu_bus_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
.init = mp_cpu_bus_init,
.acpi_fill_ssdt = generate_cpu_entries,
};
struct chip_operations northbridge_intel_sandybridge_ops = {