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soc/intel/alderlake: Hook up the OC watchdog 

Hook up the OC watchdog common block and initialize it if requested.

TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets
after some time. Enable the watchdog in driverless mode and see the
platform no longer resets and periodic SMI keeps feeding the watchdog.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I1c2c640d48b7e03ad8cd8d6cdf6aac447e93cd86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68945
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski 2022-10-28 15:53:23 +02:00 committed by Felix Held
parent 1728e1bc15
commit ce14b611d4
2 changed files with 4 additions and 0 deletions
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1
src/soc/intel/alderlake/Kconfig
View File

@ -65,6 +65,7 @@ config SOC_INTEL_ALDERLAKE
select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_IRQ
select SOC_INTEL_COMMON_BLOCK_ME_SPEC_16 select SOC_INTEL_COMMON_BLOCK_ME_SPEC_16
select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_MEMINIT
select SOC_INTEL_COMMON_BLOCK_OC_WDT
select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
select SOC_INTEL_COMMON_BLOCK_PMC_EPOC select SOC_INTEL_COMMON_BLOCK_PMC_EPOC
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT

3
src/soc/intel/alderlake/romstage/romstage.c
View File

@ -9,6 +9,7 @@
#include <intelblocks/cfg.h> #include <intelblocks/cfg.h>
#include <intelblocks/cse.h> #include <intelblocks/cse.h>
#include <intelblocks/early_graphics.h> #include <intelblocks/early_graphics.h>
#include <intelblocks/oc_wdt.h>
#include <intelblocks/pcr.h> #include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <intelblocks/smbus.h> #include <intelblocks/smbus.h>
@ -166,6 +167,8 @@ void mainboard_romstage_entry(void)
struct chipset_power_state *ps = pmc_get_power_state(); struct chipset_power_state *ps = pmc_get_power_state();
bool s3wake = pmc_fill_power_state(ps) == ACPI_S3; bool s3wake = pmc_fill_power_state(ps) == ACPI_S3;
setup_oc_wdt();
/* Initialize HECI interface */ /* Initialize HECI interface */
cse_init(HECI1_BASE_ADDRESS); cse_init(HECI1_BASE_ADDRESS);