mb/google/geralt: Move I2C and SPI initialization to verstage

After enabling VBOOT_CBFS_INTEGRATION, bootblock exceeds allocated size
(60K) by 3.5K. Since TPM and EC won't be accessed in bootblock, we move
I2C and SPI initializaion to verstage to reduce bootblock size. The GSC
interrupt pin configuration is also moved to verstage to save more
spaces for bootblock.

The size of bootblock.raw.bin is reduced from 64,040 bytes to 60,808
bytes.

BUG=b:294643742
TEST=boot to kernel

Change-Id: I5f6855d5a1a0fce6e739d44652c88e406f6f7b89
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/mainboard/google/geralt/Makefile.inc

@@ -7,6 +7,7 @@ bootblock-y += chromeos.c
 verstage-y += memlayout.ld
 verstage-y += chromeos.c
 verstage-y += reset.c
+verstage-y += verstage.c
 
 romstage-y += memlayout.ld
 romstage-y += chromeos.c

src/mainboard/google/geralt/bootblock.c

@@ -1,10 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootblock_common.h>
-#include <device/mmio.h>
 #include <gpio.h>
-#include <soc/gpio.h>
-#include <soc/i2c.h>
 #include <soc/spi.h>
 
 #include "gpio.h"
@@ -16,10 +13,7 @@ static void usb3_hub_reset(void)
 
 void bootblock_mainboard_init(void)
 {
-	mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST);
-	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
 	mtk_snfc_init();
 	setup_chromeos_gpios();
-	gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_EDGE_RISING);
 	usb3_hub_reset();
 }

src/mainboard/google/geralt/verstage.c

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <security/vboot/vboot_common.h>
+#include <soc/i2c.h>
+#include <soc/spi.h>
+
+#include "gpio.h"
+
+void verstage_mainboard_init(void)
+{
+	mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST);
+	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
+	gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_EDGE_RISING);
+}