drivers/pc80/rtc: Reorganize prototypes

Change-Id: Idea18f437c31ebe83dd61a185e614106a1f8f976
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/arch/x86/cpu.c

@@ -5,6 +5,7 @@
 #include <boot/coreboot_tables.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
+#include <post.h>
 #include <string.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/lapic.h>

src/arch/x86/post.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
+#include <post.h>
 #include <stdint.h>
 #include <console/console.h>
 #include <arch/io.h>

src/device/device.c

@@ -9,6 +9,7 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
+#include <post.h>
 #include <stdlib.h>
 #include <string.h>
 #include <smp/spinlock.h>

src/drivers/elog/elog.c

@@ -7,14 +7,12 @@
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
-#if CONFIG(ARCH_X86)
-#include <pc80/mc146818rtc.h>
-#endif
 #include <bcd.h>
 #include <boot_device.h>
 #include <commonlib/region.h>
 #include <fmap.h>
 #include <lib.h>
+#include <post.h>
 #include <rtc.h>
 #include <smbios.h>
 #include <stdint.h>

src/drivers/pc80/rtc/post.c

@@ -2,6 +2,7 @@
 /* This file is part of the coreboot project. */
 
 #include <stdint.h>
+#include <post.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <pc80/mc146818rtc.h>

src/include/console/console.h

@@ -7,6 +7,7 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <console/post_codes.h>
+#include <console/vtxprintf.h>
 
 /* console.h is supposed to provide the log levels defined in here: */
 #include <commonlib/loglevel.h>
@@ -14,31 +15,10 @@
 #define RAM_DEBUG (CONFIG(DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER)
 #define RAM_SPEW  (CONFIG(DEBUG_RAM_SETUP) ? BIOS_SPEW  : BIOS_NEVER)
 
-#include <console/vtxprintf.h>
-
-struct device;
-
 void post_code(u8 value);
-void arch_post_code(u8 value);
-void cmos_post_code(u8 value);
-void cmos_post_extra(u32 value);
-void cmos_post_path(const struct device *dev);
-int cmos_post_previous_boot(u8 *code, u32 *extra);
-
-static inline void post_log_path(const struct device *dev)
-{
-	if (CONFIG(CMOS_POST) && dev)
-		cmos_post_path(dev);
-}
-
-static inline void post_log_clear(void)
-{
-	if (CONFIG(CMOS_POST))
-		cmos_post_extra(0);
-}
-
-/* this function is weak and can be overridden by a mainboard function. */
 void mainboard_post(u8 value);
+void arch_post_code(u8 value);
+
 void __noreturn die(const char *fmt, ...);
 #define die_with_post_code(value, fmt, ...) \
 	do { post_code(value); die(fmt, ##__VA_ARGS__); } while (0)

src/include/pc80/mc146818rtc.h

@@ -183,6 +183,5 @@ void cmos_set_checksum(int range_start, int range_end, int cks_loc);
 
 #endif /* CONFIG_ARCH_X86 */
 
-void cmos_post_init(void);
 
 #endif /*  PC80_MC146818RTC_H */

src/include/post.h

@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#ifndef __POST_H__
+#define __POST_H__
+
+#include <stdint.h>
+#include <device/device.h>
+
+void cmos_post_init(void);
+void cmos_post_code(u8 value);
+void cmos_post_extra(u32 value);
+void cmos_post_path(const struct device *dev);
+int cmos_post_previous_boot(u8 *code, u32 *extra);
+
+static inline void post_log_path(const struct device *dev)
+{
+	if (CONFIG(CMOS_POST) && dev)
+		cmos_post_path(dev);
+}
+
+static inline void post_log_clear(void)
+{
+	if (CONFIG(CMOS_POST))
+		cmos_post_extra(0);
+}
+
+#endif

src/lib/bootblock.c

@@ -6,7 +6,7 @@
 #include <console/console.h>
 #include <delay.h>
 #include <option.h>
-#include <pc80/mc146818rtc.h>
+#include <post.h>
 #include <program_loading.h>
 #include <symbols.h>
 #include <timestamp.h>

src/soc/intel/xeon_sp/skx/chip.c

@@ -15,6 +15,7 @@
 
 #include <cbfs.h>
 #include <assert.h>
+#include <post.h>
 #include <device/pci.h>
 #include <soc/acpi.h>
 #include <soc/ramstage.h>