nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decoding
Other northbridges have a `decode_pcie_bar` function. Since it's not needed anywhere else, keep it as a static function for now. Change-Id: Ide42ffcebb73c3e683e0ccaf0ab3aeae805d1123 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -3,48 +3,48 @@
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#define __SIMPLE_DEVICE__
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#include <types.h>
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#include <commonlib/helpers.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include "ironlake.h"
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unsigned long acpi_fill_mcfg(unsigned long current)
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static int decode_pcie_bar(u32 *const base, u32 *const len)
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{
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u32 pciexbar = 0;
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u32 pciexbar_reg;
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int max_buses;
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*base = 0;
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*len = 0;
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pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR);
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const u32 pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR);
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// MMCFG not supported or not enabled.
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if (!(pciexbar_reg & (1 << 0)))
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return current;
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return 0;
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switch ((pciexbar_reg >> 1) & 3) {
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case 0: // 256MB
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pciexbar =
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pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
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(1 << 28));
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max_buses = 256;
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break;
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case 1: // 128M
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pciexbar =
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pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
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(1 << 28) | (1 << 27));
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max_buses = 128;
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break;
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case 2: // 64M
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pciexbar =
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pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
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(1 << 28) | (1 << 27) | (1 << 26));
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max_buses = 64;
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break;
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default: // RSVD
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return current;
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case 0: /* 256MB */
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*base = pciexbar_reg & (0x0f << 28);
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*len = 256 * MiB;
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return 1;
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case 1: /* 128M */
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*base = pciexbar_reg & (0x1f << 27);
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*len = 128 * MiB;
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return 1;
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case 2: /* 64M */
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*base = pciexbar_reg & (0x3f << 26);
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*len = 64 * MiB;
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return 1;
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}
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if (!pciexbar)
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return 0;
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}
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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u32 length, pciexbar;
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if (!decode_pcie_bar(&pciexbar, &length))
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return current;
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const int max_buses = length / MiB;
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
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pciexbar, 0x0, 0x0, max_buses - 1);
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