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nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decoding 

Other northbridges have a `decode_pcie_bar` function. Since it's not
needed anywhere else, keep it as a static function for now.

Change-Id: Ide42ffcebb73c3e683e0ccaf0ab3aeae805d1123
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-08-03 18:57:34 +02:00
parent 4a2f08c846
commit ce3e6380b9
1 changed files with 28 additions and 28 deletions
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56
src/northbridge/intel/ironlake/acpi.c
View File

@ -3,48 +3,48 @@
#define __SIMPLE_DEVICE__ #define __SIMPLE_DEVICE__
#include <types.h> #include <types.h>
#include <commonlib/helpers.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include "ironlake.h" #include "ironlake.h"
unsigned long acpi_fill_mcfg(unsigned long current) static int decode_pcie_bar(u32 *const base, u32 *const len)
{ {
u32 pciexbar = 0; *base = 0;
u32 pciexbar_reg; *len = 0;
int max_buses;
pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR); const u32 pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR);
// MMCFG not supported or not enabled.
if (!(pciexbar_reg & (1 << 0))) if (!(pciexbar_reg & (1 << 0)))
return current; return 0;
switch ((pciexbar_reg >> 1) & 3) { switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB case 0: /* 256MB */
pciexbar = *base = pciexbar_reg & (0x0f << 28);
pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | *len = 256 * MiB;
(1 << 28)); return 1;
max_buses = 256; case 1: /* 128M */
break; *base = pciexbar_reg & (0x1f << 27);
case 1: // 128M *len = 128 * MiB;
pciexbar = return 1;
pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | case 2: /* 64M */
(1 << 28) | (1 << 27)); *base = pciexbar_reg & (0x3f << 26);
max_buses = 128; *len = 64 * MiB;
break; return 1;
case 2: // 64M
pciexbar =
pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28) | (1 << 27) | (1 << 26));
max_buses = 64;
break;
default: // RSVD
return current;
} }
if (!pciexbar) return 0;
}
unsigned long acpi_fill_mcfg(unsigned long current)
{
u32 length, pciexbar;
if (!decode_pcie_bar(&pciexbar, &length))
return current; return current;
const int max_buses = length / MiB;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
pciexbar, 0x0, 0x0, max_buses - 1); pciexbar, 0x0, 0x0, max_buses - 1);