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rockchip: rk3399: add functions to configure ddrc freq 

This patch list four frequencies for ddr controller,
200MHz, 300MHz, 666MHz and 800MHz and configure
each freq by setting the DPLL dividers.

By default, the clk_ddrc is from DPLL and equals to DPLL,
so here we only need to set the DPLL clock.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot

Change-Id: Ifabe85b5dc95e3c8e3e9cbf946e12e8b06b881cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 18ec4f7d8738472fbadd60fa3c8f810f5347ffa2
Original-Change-Id: I448057542c3885068ddffa5b37d0341ee3ec04b1
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/340184
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14707
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Shunqian Zheng 2016-04-21 23:53:08 +08:00 committed by Patrick Georgi
parent a1f82a3498
commit ce60d5a139
2 changed files with 42 additions and 0 deletions
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41
src/soc/rockchip/rk3399/clock.c
View File

@ -137,6 +137,16 @@ enum {
HCLK_PERILP1_PLL_SEL_GPLL = 1,
HCLK_PERILP1_DIV_CON_MASK = 0x1f,
HCLK_PERILP1_DIV_CON_SHIFT = 0,
/* CRU_SOFTRST_CON4 */
RESETN_DDR0_REQ_MASK = 1,
RESETN_DDR0_REQ_SHIFT = 8,
RESETN_DDRPHY0_REQ_MASK = 1,
RESETN_DDRPHY0_REQ_SHIFT = 9,
RESETN_DDR1_REQ_MASK = 1,
RESETN_DDR1_REQ_SHIFT = 12,
RESETN_DDRPHY1_REQ_MASK = 1,
RESETN_DDRPHY1_REQ_SHIFT = 13,
};
#define VCO_MAX_KHZ (3200 * (MHz / KHz))
@ -350,6 +360,37 @@ void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq)
atclk_div << ATCLK_CORE_L_DIV_SHIFT));
}
void rkclk_configure_ddr(unsigned int hz)
{
struct pll_div dpll_cfg;
/* IC ECO bug, need to set this register */
write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xc000c000);
/* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
switch (hz) {
case 200*MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
break;
case 300*MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
break;
case 666*MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
break;
case 800*MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
break;
default:
die("Unsupported SDRAM frequency, add to clock.c!");
}
rkclk_set_pll(&cru_ptr->dpll_con[0], &dpll_cfg);
}
void rkclk_configure_spi(unsigned int bus, unsigned int hz)
{
}

1
src/soc/rockchip/rk3399/include/soc/clock.h
View File

@ -102,5 +102,6 @@ enum apll_l_frequencies {
void rkclk_init(void);
void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq);
void rkclk_configure_ddr(unsigned int hz);
void rkclk_configure_spi(unsigned int bus, unsigned int hz);
#endif /* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */