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soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMA 

AMD platforms require the destination buffer to be 64 byte aligned
when using the SPI DMA controller.

BUG=b:179699789
TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug
$1 = {buf = 0x0, size = 0, alignment = 64, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0}

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Raul E Rangel 2021-07-23 16:43:18 -06:00 committed by Patrick Georgi
parent 6938f353ca
commit cf17cd81d3
1 changed files with 6 additions and 0 deletions
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6
src/soc/amd/common/block/lpc/Kconfig
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@ -16,6 +16,12 @@ config SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
help help
Select this option to enable SPI DMA support. Select this option to enable SPI DMA support.
# The LPC SPI DMA controller requires the destination buffers to be 64 byte
# aligned.
config CBFS_CACHE_ALIGN
int
default 64 if SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
config SOC_AMD_COMMON_BLOCK_HAS_ESPI config SOC_AMD_COMMON_BLOCK_HAS_ESPI
bool bool
help help