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soc/intel/denverton_ns: Enable ACPI using intelblock 

- Port the existing denverton tables to intelblock
- Add C-States table for denverton

Note: Removed code is functionally identical to corresponding
common code.

Tested-on: scaleway/tagada

Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Julien Viard de Galbert 2018-04-05 11:24:45 +02:00 committed by Patrick Georgi
parent b933495229
commit cf2b72f951
11 changed files with 96 additions and 172 deletions
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15
src/mainboard/intel/harcuvar/acpi_tables.c
View File

@ -25,6 +25,7 @@
#include <device/pci.h>
#include <cpu/x86/msr.h>
#include <intelblocks/acpi.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
@ -41,17 +42,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
/* TPM Present */
gnvs->tpmp = 0;
}
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
current = acpi_create_madt_lapics(current);
/* IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2,
IO_APIC_ADDR, 0);
current = acpi_madt_irq_overrides(current);
return current;
}

24
src/mainboard/intel/harcuvar/fadt.c
View File

@ -21,30 +21,8 @@
#include <soc/acpi.h>
#include <soc/soc_util.h>
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
void motherboard_fill_fadt(acpi_fadt_t *fadt)
{
acpi_header_t *header = &(fadt->header);
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy_s(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
header->revision = 3;
memcpy_s(header->oem_id, OEM_ID, 6);
memcpy_s(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy_s(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = 1;
fadt->firmware_ctrl = (unsigned long)facs;
fadt->dsdt = (unsigned long)dsdt;
fadt->model = 1;
fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER;
fadt->x_firmware_ctl_l = (unsigned long)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (unsigned long)dsdt;
fadt->x_dsdt_h = 0;
acpi_fill_in_fadt(fadt);
header->checksum = acpi_checksum((void *)fadt, header->length);
}

15
src/mainboard/scaleway/tagada/acpi_tables.c
View File

@ -25,6 +25,7 @@
#include <device/pci.h>
#include <cpu/x86/msr.h>
#include <intelblocks/acpi.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
@ -41,17 +42,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
/* TPM Present */
gnvs->tpmp = 0;
}
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
current = acpi_create_madt_lapics(current);
/* IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2,
IO_APIC_ADDR, 0);
current = acpi_madt_irq_overrides(current);
return current;
}

25
src/mainboard/scaleway/tagada/fadt.c
View File

@ -3,6 +3,7 @@
*
* Copyright (C) 2007 - 2009 coresystems GmbH
* Copyright (C) 2014 - 2017 Intel Corporation.
* Copyright (C) 2018 Online SAS
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -21,30 +22,8 @@
#include <soc/acpi.h>
#include <soc/soc_util.h>
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
void motherboard_fill_fadt(acpi_fadt_t *fadt)
{
acpi_header_t *header = &(fadt->header);
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy_s(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
header->revision = 3;
memcpy_s(header->oem_id, OEM_ID, 6);
memcpy_s(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy_s(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = 1;
fadt->firmware_ctrl = (unsigned long)facs;
fadt->dsdt = (unsigned long)dsdt;
fadt->model = 1;
fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER;
fadt->x_firmware_ctl_l = (unsigned long)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (unsigned long)dsdt;
fadt->x_dsdt_h = 0;
acpi_fill_in_fadt(fadt);
header->checksum = acpi_checksum((void *)fadt, header->length);
}

4
src/soc/intel/common/block/acpi/acpi.c
View File

@ -31,7 +31,7 @@
#include <soc/nvs.h>
#include <soc/pm.h>
unsigned long acpi_fill_mcfg(unsigned long current)
__attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current)
{
/* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
current += acpi_create_mcfg_mmconfig((void *)current,
@ -180,6 +180,7 @@ uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
return generic_pm1_en;
}
#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
/*
* Save wake source information for calculating ACPI _SWS values
*
@ -218,6 +219,7 @@ static int acpi_fill_wake(uint32_t *pm1, uint32_t **gpe0)
return GPE0_REG_MAX;
}
#endif
__weak void acpi_create_gnvs(struct global_nvs_t *gnvs)
{

2
src/soc/intel/denverton_ns/Kconfig
View File

@ -43,8 +43,10 @@ config CPU_SPECIFIC_OPTIONS
select PCR_COMMON_IOSF_1_0
select SMP
select INTEL_DESCRIPTOR_MODE_CAPABLE
select COMMON_FADT
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_PMC
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
# select SOC_INTEL_COMMON_BLOCK_SA

159
src/soc/intel/denverton_ns/acpi.c
View File

@ -4,6 +4,7 @@
* Copyright (C) 2007 - 2009 coresystems GmbH
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2014 - 2017 Intel Corporation.
* Copyright (C) 2018 Online SAS
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -25,12 +26,54 @@
#include <device/pci.h>
#include <cbmem.h>
#include <intelblocks/acpi.h>
#include <soc/acpi.h>
#include <soc/cpu.h>
#include <soc/soc_util.h>
#include <soc/pmc.h>
#include <soc/systemagent.h>
#define MWAIT_RES(state, sub_state) \
{ \
.addrl = (((state) << 4) | (sub_state)), \
.space_id = ACPI_ADDRESS_SPACE_FIXED, \
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
}
#define CSTATE_RES(address_space, width, offset, address) \
{ \
.space_id = address_space, \
.bit_width = width, \
.bit_offset = offset, \
.addrl = address, \
}
static acpi_cstate_t cstate_map[] = {
{
/* C1 */
.ctype = 1, /* ACPI C1 */
.latency = 2,
.power = 1000,
.resource = MWAIT_RES(0, 0),
},
{
.ctype = 2, /* ACPI C2 */
.latency = 10,
.power = 10,
.resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0,
ACPI_BASE_ADDRESS + 0x14),
},
{
.ctype = 3, /* ACPI C3 */
.latency = 50,
.power = 10,
.resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0,
ACPI_BASE_ADDRESS + 0x15),
}
};
void acpi_init_gnvs(global_nvs_t *gnvs)
{
/* CPU core count */
@ -53,36 +96,20 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
gnvs->tsegl = (u32)(get_top_of_low_memory() - get_tseg_memory());
}
static int acpi_sci_irq(void)
uint32_t soc_read_sci_irq_select(void)
{
int scis, sci_irq;
struct device *dev = get_pmc_dev();
if (!dev)
return 0;
/* Determine how SCI is routed. */
scis = pci_read_config32(dev, PMC_ACPI_CNT) & PMC_ACPI_CNT_SCIS_MASK;
switch (scis) {
case PMC_ACPI_CNT_SCIS_IRQ9:
case PMC_ACPI_CNT_SCIS_IRQ10:
case PMC_ACPI_CNT_SCIS_IRQ11:
sci_irq = scis - PMC_ACPI_CNT_SCIS_IRQ9 + 9;
break;
case PMC_ACPI_CNT_SCIS_IRQ20:
case PMC_ACPI_CNT_SCIS_IRQ21:
case PMC_ACPI_CNT_SCIS_IRQ22:
case PMC_ACPI_CNT_SCIS_IRQ23:
sci_irq = scis - PMC_ACPI_CNT_SCIS_IRQ20 + 20;
break;
default:
printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
sci_irq = 9;
break;
}
return pci_read_config32(dev, PMC_ACPI_CNT);
}
printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
return sci_irq;
acpi_cstate_t *soc_get_cstate_map(size_t *entries)
{
*entries = ARRAY_SIZE(cstate_map);
return cstate_map;
}
unsigned long acpi_fill_mcfg(unsigned long current)
@ -103,38 +130,27 @@ unsigned long acpi_fill_mcfg(unsigned long current)
return current;
}
void acpi_fill_in_fadt(acpi_fadt_t *fadt)
__attribute__ ((weak)) void motherboard_fill_fadt(acpi_fadt_t *fadt)
{
}
void soc_fill_fadt(acpi_fadt_t *fadt)
{
u16 pmbase = get_pmbase();
/* System Management */
fadt->sci_int = acpi_sci_irq();
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
#else
fadt->smi_cmd = 0x00;
fadt->acpi_enable = 0x00;
fadt->acpi_disable = 0x00;
#endif
if (!IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
fadt->smi_cmd = 0x00;
fadt->acpi_enable = 0x00;
fadt->acpi_disable = 0x00;
}
/* Power Control */
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0;
fadt->pm1a_evt_blk = pmbase + PM1_STS;
fadt->pm1b_evt_blk = 0x0;
fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
fadt->pm1b_cnt_blk = 0x0;
fadt->pm2_cnt_blk = pmbase + PM2_CNT;
fadt->pm_tmr_blk = pmbase + PM1_TMR;
fadt->gpe0_blk = pmbase + GPE0_STS(GPE_STD);
fadt->gpe1_blk = 0;
/* Control Registers - Length */
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 8;
@ -228,59 +244,16 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt)
fadt->x_gpe1_blk.access_size = 0;
fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
fadt->x_gpe1_blk.addrh = 0x00;
motherboard_fill_fadt(fadt);
}
void generate_cpu_entries(struct device *device)
int soc_madt_sci_irq_polarity(int sci)
{
int core;
int pcontrol_blk = get_pmbase(), plen = 6;
int num_cpus = get_cpu_count();
for (core = 0; core < num_cpus; core++) {
if (core > 0) {
pcontrol_blk = 0;
plen = 0;
}
/* Generate processor \_PR.CPUx */
acpigen_write_processor(core, pcontrol_blk, plen);
/* Generate P-state tables */
/* Generate C-state tables */
/* Generate T-state tables */
acpigen_pop_len();
}
/* PPKG is usually used for thermal management
of the first and only package. */
acpigen_write_processor_package("PPKG", 0, num_cpus);
/* Add a method to notify processor nodes */
acpigen_write_processor_cnot(num_cpus);
}
unsigned long acpi_madt_irq_overrides(unsigned long current)
{
int sci_irq = acpi_sci_irq();
acpi_madt_irqoverride_t *irqovr;
uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL;
/* INT_SRC_OVR */
irqovr = (acpi_madt_irqoverride_t *)current;
current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
if (sci_irq >= 20)
sci_flags |= MP_IRQ_POLARITY_LOW;
if (sci >= 20)
return MP_IRQ_POLARITY_LOW;
else
sci_flags |= MP_IRQ_POLARITY_HIGH;
irqovr = (acpi_madt_irqoverride_t *)current;
current += acpi_create_madt_irqoverride(irqovr, 0, (u8)sci_irq, sci_irq,
sci_flags);
return current;
return MP_IRQ_POLARITY_HIGH;
}
unsigned long southcluster_write_acpi_tables(struct device *device,

2
src/soc/intel/denverton_ns/include/soc/acpi.h
View File

@ -23,12 +23,12 @@
void acpi_create_intel_hpet(acpi_hpet_t *hpet);
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
void acpi_fill_in_fadt(acpi_fadt_t *fadt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
void acpi_init_gnvs(global_nvs_t *gnvs);
unsigned long southcluster_write_acpi_tables(struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp);
void southcluster_inject_dsdt(struct device *device);
void motherboard_fill_fadt(acpi_fadt_t *fadt);
#endif /* _DENVERTON_NS_ACPI_H_ */

5
src/soc/intel/denverton_ns/include/soc/nvs.h
View File

@ -19,7 +19,7 @@
#ifndef _DENVERTON_NS_NVS_H_
#define _DENVERTON_NS_NVS_H_
typedef struct {
typedef struct global_nvs_t {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@ -63,9 +63,8 @@ typedef struct {
u32 tsegl; /* 0x58 - TSEG Length/Size */
u8 rsvd3[164];
} __attribute__((packed)) global_nvs_t;
} __packed global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);

6
src/soc/intel/denverton_ns/include/soc/pm.h
View File

@ -24,6 +24,12 @@
#define GPE_MAX 127
/* P-state configuration */
#define PSS_MAX_ENTRIES 15
#define PSS_RATIO_STEP 1
#define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10
struct chipset_power_state {
uint16_t pm1_sts;
uint16_t pm1_en;

11
src/soc/intel/denverton_ns/include/soc/pmc.h
View File

@ -38,6 +38,17 @@
#define PMC_ACPI_CNT_SCIS_IRQ21 0x05
#define PMC_ACPI_CNT_SCIS_IRQ22 0x06
#define PMC_ACPI_CNT_SCIS_IRQ23 0x07
#define SCI_IRQ_ADJUST 0
#define SCI_IRQ_SEL (0x07 << SCI_IRQ_ADJUST)
#define SCIS_IRQ9 0x00
#define SCIS_IRQ10 0x01
#define SCIS_IRQ11 0x02
#define SCIS_IRQ20 0x04
#define SCIS_IRQ21 0x05
#define SCIS_IRQ22 0x06
#define SCIS_IRQ23 0x07
#define PMC_PWRM_BASE 0x48 /* MEM BAR */
#define MASK_PMC_PWRM_BASE 0xfffff000 /* 4K alignment */
#define PMC_GEN_PMCON_A 0xA0