soc/intel/denverton_ns: Enable ACPI using intelblock
- Port the existing denverton tables to intelblock - Add C-States table for denverton Note: Removed code is functionally identical to corresponding common code. Tested-on: scaleway/tagada Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
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cf2b72f951
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@ -25,6 +25,7 @@
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#include <device/pci.h>
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#include <cpu/x86/msr.h>
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#include <intelblocks/acpi.h>
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#include <soc/acpi.h>
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#include <soc/nvs.h>
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@ -41,17 +42,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
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/* TPM Present */
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gnvs->tpmp = 0;
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}
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unsigned long acpi_fill_madt(unsigned long current)
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{
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/* Local APICs */
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current = acpi_create_madt_lapics(current);
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/* IOAPIC */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2,
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IO_APIC_ADDR, 0);
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current = acpi_madt_irq_overrides(current);
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return current;
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}
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@ -21,30 +21,8 @@
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#include <soc/acpi.h>
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#include <soc/soc_util.h>
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void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
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void motherboard_fill_fadt(acpi_fadt_t *fadt)
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{
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acpi_header_t *header = &(fadt->header);
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memset((void *)fadt, 0, sizeof(acpi_fadt_t));
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memcpy_s(header->signature, "FACP", 4);
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header->length = sizeof(acpi_fadt_t);
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header->revision = 3;
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memcpy_s(header->oem_id, OEM_ID, 6);
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memcpy_s(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
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memcpy_s(header->asl_compiler_id, ASLC, 4);
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header->asl_compiler_revision = 1;
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fadt->firmware_ctrl = (unsigned long)facs;
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fadt->dsdt = (unsigned long)dsdt;
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fadt->model = 1;
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fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER;
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fadt->x_firmware_ctl_l = (unsigned long)facs;
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fadt->x_firmware_ctl_h = 0;
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fadt->x_dsdt_l = (unsigned long)dsdt;
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fadt->x_dsdt_h = 0;
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acpi_fill_in_fadt(fadt);
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header->checksum = acpi_checksum((void *)fadt, header->length);
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}
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@ -25,6 +25,7 @@
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#include <device/pci.h>
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#include <cpu/x86/msr.h>
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#include <intelblocks/acpi.h>
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#include <soc/acpi.h>
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#include <soc/nvs.h>
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@ -41,17 +42,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
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/* TPM Present */
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gnvs->tpmp = 0;
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}
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unsigned long acpi_fill_madt(unsigned long current)
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{
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/* Local APICs */
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current = acpi_create_madt_lapics(current);
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/* IOAPIC */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2,
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IO_APIC_ADDR, 0);
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current = acpi_madt_irq_overrides(current);
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return current;
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}
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2007 - 2009 coresystems GmbH
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* Copyright (C) 2014 - 2017 Intel Corporation.
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* Copyright (C) 2018 Online SAS
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -21,30 +22,8 @@
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#include <soc/acpi.h>
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#include <soc/soc_util.h>
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void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
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void motherboard_fill_fadt(acpi_fadt_t *fadt)
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{
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acpi_header_t *header = &(fadt->header);
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memset((void *)fadt, 0, sizeof(acpi_fadt_t));
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memcpy_s(header->signature, "FACP", 4);
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header->length = sizeof(acpi_fadt_t);
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header->revision = 3;
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memcpy_s(header->oem_id, OEM_ID, 6);
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memcpy_s(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
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memcpy_s(header->asl_compiler_id, ASLC, 4);
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header->asl_compiler_revision = 1;
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fadt->firmware_ctrl = (unsigned long)facs;
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fadt->dsdt = (unsigned long)dsdt;
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fadt->model = 1;
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fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER;
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fadt->x_firmware_ctl_l = (unsigned long)facs;
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fadt->x_firmware_ctl_h = 0;
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fadt->x_dsdt_l = (unsigned long)dsdt;
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fadt->x_dsdt_h = 0;
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acpi_fill_in_fadt(fadt);
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header->checksum = acpi_checksum((void *)fadt, header->length);
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}
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@ -31,7 +31,7 @@
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#include <soc/nvs.h>
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#include <soc/pm.h>
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unsigned long acpi_fill_mcfg(unsigned long current)
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__attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current)
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{
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/* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
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current += acpi_create_mcfg_mmconfig((void *)current,
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@ -180,6 +180,7 @@ uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
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return generic_pm1_en;
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}
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#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE)
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/*
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* Save wake source information for calculating ACPI _SWS values
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*
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@ -218,6 +219,7 @@ static int acpi_fill_wake(uint32_t *pm1, uint32_t **gpe0)
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return GPE0_REG_MAX;
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}
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#endif
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__weak void acpi_create_gnvs(struct global_nvs_t *gnvs)
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{
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@ -43,8 +43,10 @@ config CPU_SPECIFIC_OPTIONS
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select PCR_COMMON_IOSF_1_0
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select SMP
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select COMMON_FADT
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_CPU
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select SOC_INTEL_COMMON_BLOCK_ACPI
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select SOC_INTEL_COMMON_BLOCK_PMC
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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# select SOC_INTEL_COMMON_BLOCK_SA
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@ -4,6 +4,7 @@
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* Copyright (C) 2007 - 2009 coresystems GmbH
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2014 - 2017 Intel Corporation.
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* Copyright (C) 2018 Online SAS
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -25,12 +26,54 @@
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#include <device/pci.h>
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#include <cbmem.h>
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#include <intelblocks/acpi.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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#include <soc/soc_util.h>
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#include <soc/pmc.h>
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#include <soc/systemagent.h>
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#define MWAIT_RES(state, sub_state) \
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{ \
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.addrl = (((state) << 4) | (sub_state)), \
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.space_id = ACPI_ADDRESS_SPACE_FIXED, \
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
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.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
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}
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#define CSTATE_RES(address_space, width, offset, address) \
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{ \
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.space_id = address_space, \
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.bit_width = width, \
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.bit_offset = offset, \
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.addrl = address, \
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}
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static acpi_cstate_t cstate_map[] = {
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{
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/* C1 */
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.ctype = 1, /* ACPI C1 */
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.latency = 2,
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.power = 1000,
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.resource = MWAIT_RES(0, 0),
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},
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{
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.ctype = 2, /* ACPI C2 */
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.latency = 10,
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.power = 10,
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.resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0,
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ACPI_BASE_ADDRESS + 0x14),
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},
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{
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.ctype = 3, /* ACPI C3 */
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.latency = 50,
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.power = 10,
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.resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0,
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ACPI_BASE_ADDRESS + 0x15),
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}
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};
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void acpi_init_gnvs(global_nvs_t *gnvs)
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{
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/* CPU core count */
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gnvs->tsegl = (u32)(get_top_of_low_memory() - get_tseg_memory());
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}
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static int acpi_sci_irq(void)
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uint32_t soc_read_sci_irq_select(void)
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{
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int scis, sci_irq;
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struct device *dev = get_pmc_dev();
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if (!dev)
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return 0;
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/* Determine how SCI is routed. */
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scis = pci_read_config32(dev, PMC_ACPI_CNT) & PMC_ACPI_CNT_SCIS_MASK;
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switch (scis) {
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case PMC_ACPI_CNT_SCIS_IRQ9:
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case PMC_ACPI_CNT_SCIS_IRQ10:
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case PMC_ACPI_CNT_SCIS_IRQ11:
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sci_irq = scis - PMC_ACPI_CNT_SCIS_IRQ9 + 9;
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break;
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case PMC_ACPI_CNT_SCIS_IRQ20:
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case PMC_ACPI_CNT_SCIS_IRQ21:
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case PMC_ACPI_CNT_SCIS_IRQ22:
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case PMC_ACPI_CNT_SCIS_IRQ23:
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sci_irq = scis - PMC_ACPI_CNT_SCIS_IRQ20 + 20;
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break;
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default:
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printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
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sci_irq = 9;
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break;
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}
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return pci_read_config32(dev, PMC_ACPI_CNT);
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}
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printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
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return sci_irq;
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acpi_cstate_t *soc_get_cstate_map(size_t *entries)
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{
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*entries = ARRAY_SIZE(cstate_map);
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return cstate_map;
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}
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unsigned long acpi_fill_mcfg(unsigned long current)
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return current;
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}
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void acpi_fill_in_fadt(acpi_fadt_t *fadt)
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__attribute__ ((weak)) void motherboard_fill_fadt(acpi_fadt_t *fadt)
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{
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}
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void soc_fill_fadt(acpi_fadt_t *fadt)
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{
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u16 pmbase = get_pmbase();
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/* System Management */
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fadt->sci_int = acpi_sci_irq();
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#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
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fadt->smi_cmd = APM_CNT;
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fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
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fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
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#else
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fadt->smi_cmd = 0x00;
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fadt->acpi_enable = 0x00;
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fadt->acpi_disable = 0x00;
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#endif
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if (!IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
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fadt->smi_cmd = 0x00;
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fadt->acpi_enable = 0x00;
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fadt->acpi_disable = 0x00;
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}
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/* Power Control */
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fadt->s4bios_req = 0x0;
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fadt->pstate_cnt = 0;
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fadt->pm1a_evt_blk = pmbase + PM1_STS;
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fadt->pm1b_evt_blk = 0x0;
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fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
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fadt->pm1b_cnt_blk = 0x0;
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fadt->pm2_cnt_blk = pmbase + PM2_CNT;
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fadt->pm_tmr_blk = pmbase + PM1_TMR;
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fadt->gpe0_blk = pmbase + GPE0_STS(GPE_STD);
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fadt->gpe1_blk = 0;
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/* Control Registers - Length */
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->pm2_cnt_len = 1;
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 8;
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fadt->x_gpe1_blk.access_size = 0;
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fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
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fadt->x_gpe1_blk.addrh = 0x00;
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motherboard_fill_fadt(fadt);
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}
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void generate_cpu_entries(struct device *device)
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int soc_madt_sci_irq_polarity(int sci)
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{
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int core;
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int pcontrol_blk = get_pmbase(), plen = 6;
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int num_cpus = get_cpu_count();
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for (core = 0; core < num_cpus; core++) {
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if (core > 0) {
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pcontrol_blk = 0;
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plen = 0;
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}
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/* Generate processor \_PR.CPUx */
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acpigen_write_processor(core, pcontrol_blk, plen);
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/* Generate P-state tables */
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/* Generate C-state tables */
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/* Generate T-state tables */
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acpigen_pop_len();
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}
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/* PPKG is usually used for thermal management
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of the first and only package. */
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acpigen_write_processor_package("PPKG", 0, num_cpus);
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/* Add a method to notify processor nodes */
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acpigen_write_processor_cnot(num_cpus);
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}
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unsigned long acpi_madt_irq_overrides(unsigned long current)
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{
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int sci_irq = acpi_sci_irq();
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acpi_madt_irqoverride_t *irqovr;
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uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL;
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/* INT_SRC_OVR */
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irqovr = (acpi_madt_irqoverride_t *)current;
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current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
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if (sci_irq >= 20)
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sci_flags |= MP_IRQ_POLARITY_LOW;
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if (sci >= 20)
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return MP_IRQ_POLARITY_LOW;
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else
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sci_flags |= MP_IRQ_POLARITY_HIGH;
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irqovr = (acpi_madt_irqoverride_t *)current;
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current += acpi_create_madt_irqoverride(irqovr, 0, (u8)sci_irq, sci_irq,
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sci_flags);
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return current;
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return MP_IRQ_POLARITY_HIGH;
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}
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unsigned long southcluster_write_acpi_tables(struct device *device,
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@ -23,12 +23,12 @@
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void acpi_create_intel_hpet(acpi_hpet_t *hpet);
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void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
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void acpi_fill_in_fadt(acpi_fadt_t *fadt);
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unsigned long acpi_madt_irq_overrides(unsigned long current);
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void acpi_init_gnvs(global_nvs_t *gnvs);
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unsigned long southcluster_write_acpi_tables(struct device *device,
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unsigned long current,
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struct acpi_rsdp *rsdp);
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void southcluster_inject_dsdt(struct device *device);
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void motherboard_fill_fadt(acpi_fadt_t *fadt);
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#endif /* _DENVERTON_NS_ACPI_H_ */
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@ -19,7 +19,7 @@
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#ifndef _DENVERTON_NS_NVS_H_
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#define _DENVERTON_NS_NVS_H_
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typedef struct {
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typedef struct global_nvs_t {
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/* Miscellaneous */
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u16 osys; /* 0x00 - Operating System */
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u8 smif; /* 0x02 - SMI function call ("TRAP") */
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@ -63,9 +63,8 @@ typedef struct {
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u32 tsegl; /* 0x58 - TSEG Length/Size */
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u8 rsvd3[164];
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} __attribute__((packed)) global_nvs_t;
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} __packed global_nvs_t;
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void acpi_create_gnvs(global_nvs_t *gnvs);
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#ifdef __SMM__
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/* Used in SMM to find the ACPI GNVS address */
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global_nvs_t *smm_get_gnvs(void);
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@ -24,6 +24,12 @@
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#define GPE_MAX 127
|
||||
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||||
/* P-state configuration */
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||||
#define PSS_MAX_ENTRIES 15
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||||
#define PSS_RATIO_STEP 1
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||||
#define PSS_LATENCY_TRANSITION 10
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||||
#define PSS_LATENCY_BUSMASTER 10
|
||||
|
||||
struct chipset_power_state {
|
||||
uint16_t pm1_sts;
|
||||
uint16_t pm1_en;
|
||||
|
|
|
@ -38,6 +38,17 @@
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|||
#define PMC_ACPI_CNT_SCIS_IRQ21 0x05
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||||
#define PMC_ACPI_CNT_SCIS_IRQ22 0x06
|
||||
#define PMC_ACPI_CNT_SCIS_IRQ23 0x07
|
||||
|
||||
#define SCI_IRQ_ADJUST 0
|
||||
#define SCI_IRQ_SEL (0x07 << SCI_IRQ_ADJUST)
|
||||
#define SCIS_IRQ9 0x00
|
||||
#define SCIS_IRQ10 0x01
|
||||
#define SCIS_IRQ11 0x02
|
||||
#define SCIS_IRQ20 0x04
|
||||
#define SCIS_IRQ21 0x05
|
||||
#define SCIS_IRQ22 0x06
|
||||
#define SCIS_IRQ23 0x07
|
||||
|
||||
#define PMC_PWRM_BASE 0x48 /* MEM BAR */
|
||||
#define MASK_PMC_PWRM_BASE 0xfffff000 /* 4K alignment */
|
||||
#define PMC_GEN_PMCON_A 0xA0
|
||||
|
|
Loading…
Reference in New Issue