nb/intel/i945: Use common SMM_TSEG code

Use the common SMM_TSEG code to relocate the smihandler to TSEG.

This also caches the TSEG region and therefore increases MTRR usage a
little in some cases.

This fixes S3 resume being broken introduced by CB:25594
"sb/intel/i82801gx: Use common Intel SMM code".

Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.

Tested on Intel d945gclf and Lenovo Thinkpad X60.

Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25595
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/model_106cx/Makefile.inc

@@ -1,5 +1,6 @@
 ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../common
+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
 
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin

src/cpu/intel/model_6ex/Makefile.inc

@@ -1,5 +1,6 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../common
+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
 
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin

src/cpu/intel/model_f3x/Makefile.inc

@@ -1,3 +1,4 @@
 ramstage-y += model_f3x_init.c
+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
 
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin

src/cpu/intel/model_f4x/Makefile.inc

@@ -1,3 +1,4 @@
 ramstage-y += model_f4x_init.c
+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
 
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin

src/northbridge/intel/i945/Kconfig

@@ -29,6 +29,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select POSTCAR_STAGE
 	select POSTCAR_CONSOLE
+	select SMM_TSEG
 
 config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
 	def_bool n

src/northbridge/intel/i945/northbridge.c

@@ -24,6 +24,7 @@
 #include <string.h>
 #include <cpu/cpu.h>
 #include <arch/acpi.h>
+#include <cpu/intel/smm/gen1/smi.h>
 #include "i945.h"
 
 static int get_pcie_bar(u32 *base)
@@ -154,6 +155,36 @@ static const char *northbridge_acpi_name(const struct device *dev)
 	return NULL;
 }
 
+void northbridge_write_smram(u8 smram)
+{
+	struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+
+	if (dev == NULL)
+		die("could not find pci 00:00.0!\n");
+
+	pci_write_config8(dev, SMRAM, smram);
+}
+
+/*
+ * Really doesn't belong here but will go away with parallel mp init,
+ * so let it be here for a while...
+ */
+int cpu_get_apic_id_map(int *apic_id_map)
+{
+	unsigned int i;
+
+	/* Logical processors (threads) per core */
+	const struct cpuid_result cpuid1 = cpuid(1);
+	/* Read number of cores. */
+	const char cores = (cpuid1.ebx >> 16) & 0xf;
+
+	/* TODO in parallel MP cpuid(1).ebx */
+	for (i = 0; i < cores; i++)
+		apic_id_map[i] = i;
+
+	return cores;
+}
+
 	/* TODO We could determine how many PCIe busses we need in
 	 * the bar. For now that number is hardcoded to a max of 64.
 	 * See e7525/northbridge.c for an example.

src/northbridge/intel/i945/ram_calc.c

@@ -24,6 +24,7 @@
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <program_loading.h>
+#include <cpu/intel/smm/gen1/smi.h>
 
 /* Decodes TSEG region size to bytes. */
 u32 decode_tseg_size(const u8 esmramc)
@@ -43,7 +44,7 @@ u32 decode_tseg_size(const u8 esmramc)
 	}
 }
 
-static uintptr_t smm_region_start(void)
+u32 northbridge_get_tseg_base(void)
 {
 	uintptr_t tom;
 
@@ -58,13 +59,20 @@ static uintptr_t smm_region_start(void)
 	return tom;
 }
 
-/* Depending of UMA and TSEG configuration, TSEG might start at any
+u32 northbridge_get_tseg_size(void)
+{
+	const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
+	return decode_tseg_size(esmramc);
+}
+
+/*
+ * Depending of UMA and TSEG configuration, TSEG might start at any
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
 void *cbmem_top(void)
 {
-	uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB);
+	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 	return (void *) top_of_ram;
 }
 
@@ -99,14 +107,14 @@ void platform_enter_postcar(void)
 	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
 	postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
 
-	/* Cache two separate 4 MiB regions below the top of ram, this
+	/* Cache 8 MiB region below the top of ram and 2 MiB above top of
-	 * satisfies MTRR alignment requirements. If you modify this to
+	 * ram to cover both cbmem as the TSEG region.
-	 * cover TSEG, make sure UMA region is not set with WRBACK as it
-	 * causes hard-to-recover boot failures.
 	 */
 	top_of_ram = (uintptr_t)cbmem_top();
-	postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
-	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
+			MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
+			       northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
 
 	run_postcar_phase(&pcf);
 

src/southbridge/intel/i82801gx/Makefile.inc

@@ -32,8 +32,10 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
 ramstage-y += watchdog.c
 
+ifneq ($(CONFIG_SMM_TSEG),y)
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
+endif
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
 romstage-y += early_smbus.c early_lpc.c