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soc/intel/alderlake: Add minimal ACPI support for PEG ports 

Add minimal Device entries with just an _ADR for each of the PEG ports
for P and M chipsets (N does not have any PEG ports).

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Id1009004969729eddf7005fa190f5e1ca2d7b468
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Tim Wawrzynczak 2021-12-16 15:01:44 -07:00
parent 40c9c8aa80
commit cf39336ccf
2 changed files with 22 additions and 0 deletions
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19
src/soc/intel/alderlake/acpi/pcie.asl
View File

@ -299,3 +299,22 @@ Device (RP12)
Return (IRQM (RPPN))
}
}
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_P)
Device (PEG0)
{
Name (_ADR, 0x00060000)
}
#endif
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P)
Device (PEG1)
{
Name (_ADR, 0x00060002)
}
Device (PEG2)
{
Name (_ADR, 0x00010000)
}
#endif

3
src/soc/intel/alderlake/chip.c
View File

@ -61,6 +61,9 @@ const char *soc_acpi_name(const struct device *dev)
switch (dev->path.pci.devfn) {
case SA_DEVFN_ROOT: return "MCHC";
case SA_DEVFN_CPU_PCIE1_0: return "PEG2";
case SA_DEVFN_CPU_PCIE6_0: return "PEG0";
case SA_DEVFN_CPU_PCIE6_2: return "PEG1";
case SA_DEVFN_IGD: return "GFX0";
case SA_DEVFN_TCSS_XHCI: return "TXHC";
case SA_DEVFN_TCSS_XDCI: return "TXDC";