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mb/google/skyrim: Add "Normal" DPTC values 

Add the Normal Mode DPTC values for Skyrim.

These values were generated by AMD.

BRANCH=none
BUG=b:217911928
TEST=Build skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I1e1f55b941f3e70aad33d55a90fb012eac3ba12d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67690
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Van Patten 2022-09-06 09:56:52 -06:00 committed by Martin L Roth
parent b06873f77c
commit cf9e0a08f5
1 changed files with 12 additions and 0 deletions
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12
src/mainboard/google/skyrim/variants/skyrim/overridetree.cb
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@ -245,4 +245,16 @@ chip soc/amd/mendocino
end
end # UART1
# Normal
# These registers are defined in AMD DevHub document #57316.
register "slow_ppt_limit_mW" = "25000"
register "fast_ppt_limit_mW" = "30000"
register "slow_ppt_time_constant_s" = "5"
register "stapm_time_constant_s" = "275"
register "sustained_power_limit_mW" = "15000"
register "thermctl_limit_degreeC" = "100"
register "vrm_current_limit_mA" = "28000"
register "vrm_maximum_current_limit_mA" = "50000"
register "vrm_soc_current_limit_mA" = "10000"
end # chip soc/amd/mendocino