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mb/intel/shadowmountain: Add the ASL code 

This reverts commit d510b60f5b.

This patch includes the DSDT ASL code for shadowmountain board.

BUG=b:175808146
TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5aa60730fc9b93fa97b2bafbb8b2714b6b37becc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
V Sowmya 2021-02-22 08:47:06 +05:30 committed by Patrick Georgi
parent ae930d85c2
commit cfb1bf2275
1 changed files with 28 additions and 0 deletions
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28
src/mainboard/intel/shadowmountain/dsdt.asl
View File

@ -1,6 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
#include <baseboard/ec.h>
#include <baseboard/gpio.h>
DefinitionBlock(
"dsdt.aml",
@ -12,4 +14,30 @@ DefinitionBlock(
)
{
#include <acpi/dsdt_top.asl>
#include <soc/intel/common/block/acpi/acpi/platform.asl>
/* global NVS and variables */
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/alderlake/acpi/southbridge.asl>
#include <soc/intel/alderlake/acpi/tcss.asl>
}
}
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
// ACPI code for EC SuperIO functions
#include <ec/google/chromeec/acpi/superio.asl>
// ACPI code for EC functions
#include <ec/google/chromeec/acpi/ec.asl>
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
}