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soc/intel/alderlake: Add HID for DPTF Power Participant 

BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check TPWR device HID

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I82507a3c0a521adbb8dec5520fd6d2ea3782c60e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Varshit B Pandya 2022-03-29 18:16:20 +05:30 committed by Paul Fagerburg
parent e7d3a1a9e8
commit d025ab3bc2
1 changed files with 2 additions and 0 deletions
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src/soc/intel/alderlake/dptf.c
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@ -12,6 +12,8 @@ static const struct dptf_platform_info adl_dptf_platform_info = {
.fan_hid = "INTC1048", .fan_hid = "INTC1048",
/* _HID for the toplevel TPCH device, typically \_SB.TPCH */ /* _HID for the toplevel TPCH device, typically \_SB.TPCH */
.tpch_device_hid = "INTC1049", .tpch_device_hid = "INTC1049",
/* _HID for the toplevel TPWR device, typically \_SB.DPTF.TPWR */
.tpwr_device_hid = "INTC1060",
.tpch_method_names = { .tpch_method_names = {
.set_fivr_low_clock_method = "RFC0", .set_fivr_low_clock_method = "RFC0",