sb/intel/ibexpeak: Implement PCH function disable in chip_ops
This does the following: - implement a PCH disable function that will be called by the PCI drivers as part of their chip_ops - removes the iobp_x calls as those don't exist on ibexpeak - complete the devicetree with to be disabled PCI devices for the chip_ops to be called - Clean up some code copied from bd82x6x Change-Id: I78d25ffe9af482c77d397a9fdb4f0127e40baddc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans
parent
f266dc6174
commit
d0310faa3b
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@ -74,9 +74,10 @@ chip northbridge/intel/nehalem
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register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
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device pci 16.2 on # IDE/SATA
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subsystemid 0x17aa 0x2161
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end
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R, only management boot
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 on # Ethernet
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subsystemid 0x17aa 0x2153
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@ -92,14 +93,19 @@ chip northbridge/intel/nehalem
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2 (wwan)
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device pci 1c.2 off end
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device pci 1c.3 on
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smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
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end # PCIe Port #4 (Expresscard)
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device pci 1c.4 on end # PCIe Port #5 (wlan)
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device pci 1c.5 off end
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device pci 1c.6 off end
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device pci 1c.7 off end
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device pci 1d.0 on # USB2 EHCI
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subsystemid 0x17aa 0x2163
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end
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device pci 1e.0 on end # PCI 2 PCI bridge
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device pci 1f.0 on # PCI-LPC bridge
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subsystemid 0x17aa 0x2166
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chip superio/nsc/pc87382
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@ -179,6 +185,9 @@ chip northbridge/intel/nehalem
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device i2c 5f on end
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end
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end
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device pci 1f.4 off end
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device pci 1f.5 off end
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device pci 1f.6 on end
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end
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end
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end
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@ -66,6 +66,13 @@ chip northbridge/intel/nehalem
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register "alt_gp_smi_en" = "0x0000"
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register "gen1_dec" = "0x040069"
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R, only management boot
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 off end # Ethernet
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device pci 1a.0 on # USB2 EHCI
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subsystemid 0x1025 0x0379
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end
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@ -75,11 +82,18 @@ chip northbridge/intel/nehalem
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end
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2
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device pci 1c.2 off end
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device pci 1c.3 off end
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device pci 1c.4 off end
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device pci 1c.5 off end
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device pci 1c.6 off end
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device pci 1c.7 off end
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device pci 1d.0 on # USB2 EHCI
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subsystemid 0x1025 0x0379
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end
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device pci 1e.0 on end # PCI 2 PCI bridge
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device pci 1f.0 on # PCI-LPC bridge
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subsystemid 0x1025 0x0379
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end
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@ -89,6 +103,9 @@ chip northbridge/intel/nehalem
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device pci 1f.3 on # SMBUS
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subsystemid 0x1025 0x0379
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end
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device pci 1f.4 off end
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device pci 1f.5 off end
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device pci 1f.6 off end
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end
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end
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end
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@ -15,7 +15,7 @@
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ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y)
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ramstage-y += ../bd82x6x/pch.c
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ramstage-y += pch.c
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ramstage-y += azalia.c
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ramstage-y += lpc.c
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ramstage-y += ../bd82x6x/pci.c
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@ -35,7 +35,7 @@ ramstage-y += ../bd82x6x/me_status.c
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ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c
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ramstage-y += madt.c
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smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/pch.c
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smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c
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romstage-y += early_smbus.c
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romstage-y +=../bd82x6x/early_me.c
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@ -409,11 +409,6 @@ static void enable_clock_gating(struct device *dev)
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reg16 |= (1 << 2) | (1 << 11);
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pci_write_config16(dev, GEN_PMCON_1, reg16);
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pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
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pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
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pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
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pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
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reg32 = RCBA32(CG);
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reg32 |= (1 << 31);
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reg32 |= (1 << 29) | (1 << 28);
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@ -500,13 +495,7 @@ static void lpc_init(struct device *dev)
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pch_power_options(dev);
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/* Initialize power management */
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switch (pch_silicon_type()) {
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case PCH_TYPE_MOBILE5:
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mobile5_pm_init (dev);
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break;
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default:
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printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device);
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}
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mobile5_pm_init(dev);
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/* Set the state of the GPIO lines. */
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//gpio_init(dev);
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@ -0,0 +1,107 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include "pch.h"
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/* Set bit in function disable register to hide this device */
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static void pch_disable_devfn(struct device *dev)
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{
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switch (dev->path.pci.devfn) {
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case PCI_DEVFN(22, 0): /* MEI #1 */
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RCBA32_OR(FD2, PCH_DISABLE_MEI1);
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break;
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case PCI_DEVFN(22, 1): /* MEI #2 */
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RCBA32_OR(FD2, PCH_DISABLE_MEI2);
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break;
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case PCI_DEVFN(22, 2): /* IDE-R */
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RCBA32_OR(FD2, PCH_DISABLE_IDER);
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break;
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case PCI_DEVFN(22, 3): /* KT */
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RCBA32_OR(FD2, PCH_DISABLE_KT);
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break;
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case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
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RCBA32_OR(BUC, PCH_DISABLE_GBE);
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break;
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case PCI_DEVFN(26, 0): /* EHCI #2 */
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RCBA32_OR(FD, PCH_DISABLE_EHCI2);
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break;
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case PCI_DEVFN(27, 0): /* HD Audio Controller */
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RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
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break;
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case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
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case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
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case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
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case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
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case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
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case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
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case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
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case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
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RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn)));
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break;
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case PCI_DEVFN(29, 0): /* EHCI #1 */
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RCBA32_OR(FD, PCH_DISABLE_EHCI1);
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break;
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case PCI_DEVFN(31, 0): /* LPC */
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RCBA32_OR(FD, PCH_DISABLE_LPC);
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break;
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case PCI_DEVFN(31, 2): /* SATA #1 */
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RCBA32_OR(FD, PCH_DISABLE_SATA1);
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break;
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case PCI_DEVFN(31, 3): /* SMBUS */
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RCBA32_OR(FD, PCH_DISABLE_SMBUS);
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break;
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case PCI_DEVFN(31, 5): /* SATA #22 */
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RCBA32_OR(FD, PCH_DISABLE_SATA2);
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break;
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case PCI_DEVFN(31, 6): /* Thermal Subsystem */
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RCBA32_OR(FD, PCH_DISABLE_THERMAL);
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break;
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}
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}
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void pch_enable(struct device *dev)
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{
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u32 reg32;
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if (!dev->enabled) {
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printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
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/* Ensure memory, io, and bus master are all disabled */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 &= ~(PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* Disable this device if possible */
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pch_disable_devfn(dev);
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} else {
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/* Enable SERR */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 |= PCI_COMMAND_SERR;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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}
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}
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struct chip_operations southbridge_intel_ibexpeak_ops = {
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CHIP_NAME("Intel Series 5 (Ibexpeak) Southbridge")
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.enable_dev = pch_enable,
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};
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@ -51,9 +51,6 @@
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#ifndef __ACPI__
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#define DEBUG_PERIODIC_SMIS 0
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int pch_silicon_revision(void);
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int pch_silicon_type(void);
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int pch_silicon_supported(int type, int rev);
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void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
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void enable_smbus(void);
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void enable_usb_bar(void);
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@ -176,15 +176,6 @@ static void sata_init(struct device *dev)
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sata_port_map ^ 0x3f) << 24) | 0x183);
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}
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/* Set Gen3 Transmitter settings if needed */
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if (config->sata_port0_gen3_tx)
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pch_iobp_update(SATA_IOBP_SP0G3IR, 0,
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config->sata_port0_gen3_tx);
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if (config->sata_port1_gen3_tx)
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pch_iobp_update(SATA_IOBP_SP1G3IR, 0,
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config->sata_port1_gen3_tx);
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/* Additional Programming Requirements */
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sir_write(dev, 0x04, 0x00000000);
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sir_write(dev, 0x28, 0x0a000033);
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@ -208,9 +199,6 @@ static void sata_init(struct device *dev)
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sir_write(dev, 0xc4, 0x0c0c0c0c);
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sir_write(dev, 0xc8, 0x0c0c0c0c);
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sir_write(dev, 0xd4, 0x10000000);
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pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
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pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
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}
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static void sata_enable(struct device *dev)
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