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sb/intel/ibexpeak: Implement PCH function disable in chip_ops 

This does the following:
- implement a PCH disable function that will be called by the PCI
  drivers as part of their chip_ops
- removes the iobp_x calls as those don't exist on ibexpeak
- complete the devicetree with to be disabled PCI devices for the
  chip_ops to be called
- Clean up some code copied from bd82x6x

Change-Id: I78d25ffe9af482c77d397a9fdb4f0127e40baddc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans 2019-10-02 00:21:01 +02:00
parent f266dc6174
commit d0310faa3b
7 changed files with 140 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
src/mainboard/lenovo/x201/devicetree.cb
View File

@ -74,9 +74,10 @@ chip northbridge/intel/nehalem
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
device pci 16.2 on # IDE/SATA
subsystemid 0x17aa 0x2161
end
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R, only management boot
device pci 16.3 off end # Management Engine KT
device pci 19.0 on # Ethernet
subsystemid 0x17aa 0x2153
@ -92,14 +93,19 @@ chip northbridge/intel/nehalem
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 on end # PCIe Port #2 (wwan)
device pci 1c.2 off end
device pci 1c.3 on
smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
end # PCIe Port #4 (Expresscard)
device pci 1c.4 on end # PCIe Port #5 (wlan)
device pci 1c.5 off end
device pci 1c.6 off end
device pci 1c.7 off end
device pci 1d.0 on # USB2 EHCI
subsystemid 0x17aa 0x2163
end
device pci 1e.0 on end # PCI 2 PCI bridge
device pci 1f.0 on # PCI-LPC bridge
subsystemid 0x17aa 0x2166
chip superio/nsc/pc87382
@ -179,6 +185,9 @@ chip northbridge/intel/nehalem
device i2c 5f on end
end
end
device pci 1f.4 off end
device pci 1f.5 off end
device pci 1f.6 on end
end
end
end

19
src/mainboard/packardbell/ms2290/devicetree.cb
View File

@ -66,6 +66,13 @@ chip northbridge/intel/nehalem
register "alt_gp_smi_en" = "0x0000"
register "gen1_dec" = "0x040069"
device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R, only management boot
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Ethernet
device pci 1a.0 on # USB2 EHCI
subsystemid 0x1025 0x0379
end
@ -75,11 +82,18 @@ chip northbridge/intel/nehalem
end
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 on end # PCIe Port #1
device pci 1c.1 on end # PCIe Port #2
device pci 1c.2 off end
device pci 1c.3 off end
device pci 1c.4 off end
device pci 1c.5 off end
device pci 1c.6 off end
device pci 1c.7 off end
device pci 1d.0 on # USB2 EHCI
subsystemid 0x1025 0x0379
end
device pci 1e.0 on end # PCI 2 PCI bridge
device pci 1f.0 on # PCI-LPC bridge
subsystemid 0x1025 0x0379
end
@ -89,6 +103,9 @@ chip northbridge/intel/nehalem
device pci 1f.3 on # SMBUS
subsystemid 0x1025 0x0379
end
device pci 1f.4 off end
device pci 1f.5 off end
device pci 1f.6 off end
end
end
end

4
src/southbridge/intel/ibexpeak/Makefile.inc
View File

@ -15,7 +15,7 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y)
ramstage-y += ../bd82x6x/pch.c
ramstage-y += pch.c
ramstage-y += azalia.c
ramstage-y += lpc.c
ramstage-y += ../bd82x6x/pci.c
@ -35,7 +35,7 @@ ramstage-y += ../bd82x6x/me_status.c
ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c
ramstage-y += madt.c
smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/pch.c
smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c
romstage-y += early_smbus.c
romstage-y +=../bd82x6x/early_me.c

11
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -409,11 +409,6 @@ static void enable_clock_gating(struct device *dev)
reg16 |= (1 << 2) | (1 << 11);
pci_write_config16(dev, GEN_PMCON_1, reg16);
pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
reg32 = RCBA32(CG);
reg32 |= (1 << 31);
reg32 |= (1 << 29) | (1 << 28);
@ -500,13 +495,7 @@ static void lpc_init(struct device *dev)
pch_power_options(dev);
/* Initialize power management */
switch (pch_silicon_type()) {
case PCH_TYPE_MOBILE5:
mobile5_pm_init(dev);
break;
default:
printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device);
}
/* Set the state of the GPIO lines. */
//gpio_init(dev);

107
src/southbridge/intel/ibexpeak/pch.c Normal file
View File

@ -0,0 +1,107 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include "pch.h"
/* Set bit in function disable register to hide this device */
static void pch_disable_devfn(struct device *dev)
{
switch (dev->path.pci.devfn) {
case PCI_DEVFN(22, 0): /* MEI #1 */
RCBA32_OR(FD2, PCH_DISABLE_MEI1);
break;
case PCI_DEVFN(22, 1): /* MEI #2 */
RCBA32_OR(FD2, PCH_DISABLE_MEI2);
break;
case PCI_DEVFN(22, 2): /* IDE-R */
RCBA32_OR(FD2, PCH_DISABLE_IDER);
break;
case PCI_DEVFN(22, 3): /* KT */
RCBA32_OR(FD2, PCH_DISABLE_KT);
break;
case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
RCBA32_OR(BUC, PCH_DISABLE_GBE);
break;
case PCI_DEVFN(26, 0): /* EHCI #2 */
RCBA32_OR(FD, PCH_DISABLE_EHCI2);
break;
case PCI_DEVFN(27, 0): /* HD Audio Controller */
RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
break;
case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn)));
break;
case PCI_DEVFN(29, 0): /* EHCI #1 */
RCBA32_OR(FD, PCH_DISABLE_EHCI1);
break;
case PCI_DEVFN(31, 0): /* LPC */
RCBA32_OR(FD, PCH_DISABLE_LPC);
break;
case PCI_DEVFN(31, 2): /* SATA #1 */
RCBA32_OR(FD, PCH_DISABLE_SATA1);
break;
case PCI_DEVFN(31, 3): /* SMBUS */
RCBA32_OR(FD, PCH_DISABLE_SMBUS);
break;
case PCI_DEVFN(31, 5): /* SATA #22 */
RCBA32_OR(FD, PCH_DISABLE_SATA2);
break;
case PCI_DEVFN(31, 6): /* Thermal Subsystem */
RCBA32_OR(FD, PCH_DISABLE_THERMAL);
break;
}
}
void pch_enable(struct device *dev)
{
u32 reg32;
if (!dev->enabled) {
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* Ensure memory, io, and bus master are all disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Disable this device if possible */
pch_disable_devfn(dev);
} else {
/* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
}
}
struct chip_operations southbridge_intel_ibexpeak_ops = {
CHIP_NAME("Intel Series 5 (Ibexpeak) Southbridge")
.enable_dev = pch_enable,
};

3
src/southbridge/intel/ibexpeak/pch.h
View File

@ -51,9 +51,6 @@
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
int pch_silicon_revision(void);
int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
void enable_smbus(void);
void enable_usb_bar(void);

12
src/southbridge/intel/ibexpeak/sata.c
View File

@ -176,15 +176,6 @@ static void sata_init(struct device *dev)
sata_port_map ^ 0x3f) << 24) | 0x183);
}
/* Set Gen3 Transmitter settings if needed */
if (config->sata_port0_gen3_tx)
pch_iobp_update(SATA_IOBP_SP0G3IR, 0,
config->sata_port0_gen3_tx);
if (config->sata_port1_gen3_tx)
pch_iobp_update(SATA_IOBP_SP1G3IR, 0,
config->sata_port1_gen3_tx);
/* Additional Programming Requirements */
sir_write(dev, 0x04, 0x00000000);
sir_write(dev, 0x28, 0x0a000033);
@ -208,9 +199,6 @@ static void sata_init(struct device *dev)
sir_write(dev, 0xc4, 0x0c0c0c0c);
sir_write(dev, 0xc8, 0x0c0c0c0c);
sir_write(dev, 0xd4, 0x10000000);
pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
}
static void sata_enable(struct device *dev)