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soc/intel/skylake: Enable CHAP device depending on devicetree 

Now that CHAP device is declared in chipset devicetree, hook it up to
devicetree configuration.

Change-Id: Icc51f7b9cda32d5058dce958e386921b6d3d8ffb
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48323
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Benjamin Doron 2020-12-07 22:56:47 +00:00 committed by Hung-Te Lin
parent b8cb142ccd
commit d0701c96f2
2 changed files with 7 additions and 0 deletions
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3
src/soc/intel/skylake/chip.c
View File

@ -247,6 +247,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
dev = pcidev_path_on_root(SA_DEVFN_IMGU); dev = pcidev_path_on_root(SA_DEVFN_IMGU);
params->SaImguEnable = dev && dev->enabled; params->SaImguEnable = dev && dev->enabled;
dev = pcidev_path_on_root(SA_DEVFN_CHAP);
tconfig->ChapDeviceEnable = dev && dev->enabled;
dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); dev = pcidev_path_on_root(PCH_DEVFN_CSE_3);
params->Heci3Enabled = dev && dev->enabled; params->Heci3Enabled = dev && dev->enabled;

4
src/soc/intel/skylake/include/soc/pci_devs.h
View File

@ -42,6 +42,10 @@
#define SA_DEVFN_IMGU PCI_DEVFN(SA_DEV_SLOT_IMGU, 0) #define SA_DEVFN_IMGU PCI_DEVFN(SA_DEV_SLOT_IMGU, 0)
#define SA_DEV_IMGU PCI_DEV(0, SA_DEV_SLOT_IMGU, 0) #define SA_DEV_IMGU PCI_DEV(0, SA_DEV_SLOT_IMGU, 0)
#define SA_DEV_SLOT_CHAP 0x07
#define SA_DEVFN_CHAP PCI_DEVFN(SA_DEV_SLOT_CHAP, 0)
#define SA_DEV_CHAP PCI_DEV(0, SA_DEV_SLOT_CHAP, 0)
#define SA_DEV_SLOT_GMM 0x08 #define SA_DEV_SLOT_GMM 0x08
#define SA_DEVFN_GMM PCI_DEVFN(SA_DEV_SLOT_GMM, 0) #define SA_DEVFN_GMM PCI_DEVFN(SA_DEV_SLOT_GMM, 0)
#define SA_DEV_GMM PCI_DEV(0, SA_DEV_SLOT_GMM, 0) #define SA_DEV_GMM PCI_DEV(0, SA_DEV_SLOT_GMM, 0)