soc/amd/genoa: rename to genoa_poc

Even though this SoC is called 'Genoa', the openSIL implementation and
the corresponding coreboot integration is only a proof of concept that
isn't fully featured, has known limitations and bugs, and is not meant
for or ready to being productized. Adding the proof of concept suffix to
the name should point this out clearly enough so that no potential
customer could infer that this might be a fully functional and supported
implementation which it is not.

Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/amd/onyx/Kconfig

@@ -2,7 +2,7 @@ if BOARD_AMD_ONYX
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select SOC_AMD_GENOA
+	select SOC_AMD_GENOA_POC
 	select BOARD_ROMSIZE_KB_32768
 	select AMD_SOC_CONSOLE_UART
 

src/mainboard/amd/onyx/devicetree.cb

@@ -1,4 +1,4 @@
-chip soc/amd/genoa
+chip soc/amd/genoa_poc
 
 	# USB configuration
 	register "usb.xhci0_enable" = "1"

src/soc/amd/genoa/include/soc/soc_chip.h

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SOC_GENOA_SOC_CHIP_H_
-#define _SOC_GENOA_SOC_CHIP_H_
-
-#include "../../chip.h"
-
-#endif

src/soc/amd/genoa_poc/Kconfig

@@ -1,7 +1,7 @@
-config SOC_AMD_GENOA
+config SOC_AMD_GENOA_POC
 	bool
 
-if SOC_AMD_GENOA
+if SOC_AMD_GENOA_POC
 
 config SOC_SPECIFIC_OPTIONS
 	def_bool y
@@ -51,7 +51,7 @@ config USE_EXP_X86_64_SUPPORT
 
 config CHIPSET_DEVICETREE
 	string
-	default "soc/amd/genoa/chipset.cb"
+	default "soc/amd/genoa_poc/chipset.cb"
 
 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
@@ -124,7 +124,7 @@ menu "PSP Configuration Options"
 
 config AMDFW_CONFIG_FILE
 	string
-	default "src/soc/amd/genoa/fw.cfg"
+	default "src/soc/amd/genoa_poc/fw.cfg"
 
 config PSP_DISABLE_POSTCODES
 	bool "Disable PSP post codes"
@@ -209,4 +209,4 @@ config ACPI_BERT_SIZE
 	  Specify the amount of DRAM reserved for gathering the data used to
 	  generate the ACPI table.
 
-endif # SOC_AMD_GENOA
+endif # SOC_AMD_GENOA_POC

src/soc/amd/genoa_poc/Makefile.inc

@@ -1,5 +1,5 @@
 ## SPDX-License-Identifier: GPL-2.0-only
-ifeq ($(CONFIG_SOC_AMD_GENOA),y)
+ifeq ($(CONFIG_SOC_AMD_GENOA_POC),y)
 
 all-y		+= mmap_boot.c
 all-y		+= reset.c
@@ -25,8 +25,8 @@ ramstage-y	+= mca.c
 
 smm-y		+= smihandler.c
 
-CPPFLAGS_common += -I$(src)/soc/amd/genoa/acpi
-CPPFLAGS_common += -I$(src)/soc/amd/genoa/include
+CPPFLAGS_common += -I$(src)/soc/amd/genoa_poc/acpi
+CPPFLAGS_common += -I$(src)/soc/amd/genoa_poc/include
 
 ifeq ($(call int-gt, $(CONFIG_ROM_SIZE) 0x1000000), 1)
 CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0:0xff000000:0x1000000

src/soc/amd/genoa_poc/acpi/globalnvs.asl

@@ -2,7 +2,7 @@
 
 /*
  * NOTE: The layout of the GNVS structure below must match the layout in
- * soc/amd/genoa/include/soc/nvs.h !!!
+ * soc/amd/genoa_poc/include/soc/nvs.h !!!
  */
 
 Field (GNVS, ByteAcc, NoLock, Preserve)

src/soc/amd/genoa_poc/chip.c

@@ -13,8 +13,8 @@ static void soc_final(void *chip_info)
 {
 }
 
-struct chip_operations soc_amd_genoa_ops = {
-	CHIP_NAME("AMD Genoa SoC")
+struct chip_operations soc_amd_genoa_poc_ops = {
+	CHIP_NAME("AMD Genoa SoC Proof of Concept")
 	.init = soc_init,
 	.final = soc_final,
 };

src/soc/amd/genoa_poc/chip.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __GENOA_CHIP_H__
-#define __GENOA_CHIP_H__
+#ifndef __GENOA_POC_CHIP_H__
+#define __GENOA_POC_CHIP_H__
 
 #include <amdblocks/chip.h>
 #include <amdblocks/i2c.h>
@@ -60,7 +60,7 @@ struct soc_usb_config {
 
 };
 
-struct soc_amd_genoa_config {
+struct soc_amd_genoa_poc_config {
 	struct soc_amd_common_config common_config;
 
 	u8 i2c_scl_reset;
@@ -69,4 +69,4 @@ struct soc_amd_genoa_config {
 	struct soc_usb_config usb;
 };
 
-#endif
+#endif /* __GENOA_POC_CHIP_H__ */

src/soc/amd/genoa_poc/chipset.cb

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-chip soc/amd/genoa
+chip soc/amd/genoa_poc
 	device cpu_cluster 0 on ops amd_cpu_bus_ops end
 
 	# OC pins

src/soc/amd/genoa_poc/config.c

@@ -7,6 +7,6 @@
 
 const struct soc_amd_common_config *soc_get_common_config(void)
 {
-	const struct soc_amd_genoa_config *cfg = config_of_soc();
+	const struct soc_amd_genoa_poc_config *cfg = config_of_soc();
 	return &cfg->common_config;
 }

src/soc/amd/genoa_poc/i2c.c

@@ -27,7 +27,7 @@ static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
 
 void reset_i2c_peripherals(void)
 {
-	const struct soc_amd_genoa_config *cfg = config_of_soc();
+	const struct soc_amd_genoa_poc_config *cfg = config_of_soc();
 	struct soc_i2c_peripheral_reset_info reset_info;
 
 	reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
@@ -49,7 +49,7 @@ const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
 
 const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses)
 {
-	const struct soc_amd_genoa_config *config = config_of_soc();
+	const struct soc_amd_genoa_poc_config *config = config_of_soc();
 
 	*num_buses = ARRAY_SIZE(config->i2c);
 	return config->i2c;

src/soc/amd/genoa_poc/include/soc/acpi.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#ifndef AMD_GENOA_ACPI_H
-#define AMD_GENOA_ACPI_H
+#ifndef AMD_GENOA_POC_ACPI_H
+#define AMD_GENOA_POC_ACPI_H
 
 #include <acpi/acpi.h>
 #include <device/device.h>
@@ -11,4 +11,4 @@
 unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current,
 				    struct acpi_rsdp *rsdp);
 
-#endif /* AMD_GENOA_ACPI_H */
+#endif /* AMD_GENOA_POC_ACPI_H */

src/soc/amd/genoa_poc/include/soc/amd_pci_int_defs.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_AMD_PCI_INT_DEFS_H
-#define AMD_GENOA_AMD_PCI_INT_DEFS_H
+#ifndef AMD_GENOA_POC_AMD_PCI_INT_DEFS_H
+#define AMD_GENOA_POC_AMD_PCI_INT_DEFS_H
 
 /*
  *  * PIRQ and device routing - these define the index into the
@@ -53,4 +53,4 @@
 #define PIRQ_UART2	0x78	/* UART2 */
 #define PIRQ_UART3	0x79	/* UART3 */
 
-#endif /* AMD_GENOA_AMD_PCI_INT_DEFS_H */
+#endif /* AMD_GENOA_POC_AMD_PCI_INT_DEFS_H */

src/soc/amd/genoa_poc/include/soc/aoac_defs.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_AOAC_DEFS_H
-#define AMD_GENOA_AOAC_DEFS_H
+#ifndef AMD_GENOA_POC_AOAC_DEFS_H
+#define AMD_GENOA_POC_AOAC_DEFS_H
 
 /* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
 #define FCH_AOAC_DEV_CLK_GEN		0
@@ -17,4 +17,4 @@
 #define FCH_AOAC_DEV_AMBA		17
 #define FCH_AOAC_DEV_ESPI		27
 
-#endif /* AMD_GENOA_AOAC_DEFS_H */
+#endif /* AMD_GENOA_POC_AOAC_DEFS_H */

src/soc/amd/genoa_poc/include/soc/cpu.h

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_CPU_H
-#define AMD_GENOA_CPU_H
+#ifndef AMD_GENOA_POC_CPU_H
+#define AMD_GENOA_POC_CPU_H
 
 #define GENOA_A0_CPUID		CPUID_FROM_FMS(0x19, 0x10, 0)
 #define GENOA_B0_CPUID		CPUID_FROM_FMS(0x19, 0x11, 0)
 
-#endif /* AMD_GENOA_CPU_H */
+#endif /* AMD_GENOA_POC_CPU_H */

src/soc/amd/genoa_poc/include/soc/data_fabric.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_DATA_FABRIC_H
-#define AMD_GENOA_DATA_FABRIC_H
+#ifndef AMD_GENOA_POC_DATA_FABRIC_H
+#define AMD_GENOA_POC_DATA_FABRIC_H
 
 #include <amdblocks/data_fabric_defs.h>
 #include <types.h>
@@ -135,4 +135,4 @@ union df_ficaa {
 	uint32_t raw;
 };
 
-#endif /* AMD_GENOA_DATA_FABRIC_H */
+#endif /* AMD_GENOA_POC_DATA_FABRIC_H */

src/soc/amd/genoa_poc/include/soc/gpio.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_GPIO_H
-#define AMD_GENOA_GPIO_H
+#ifndef AMD_GENOA_POC_GPIO_H
+#define AMD_GENOA_POC_GPIO_H
 
 #define GPIO_DEVICE_NAME	"AMDI0030"
 #define GPIO_DEVICE_DESC	"GPIO Controller"
@@ -267,4 +267,4 @@
 #define GPIO_266_IOMUX_PCIE_RST0_L 0
 #define GPIO_266_IOMUX_GPIOxx 1
 
-#endif /* AMD_GENOA_GPIO_H */
+#endif /* AMD_GENOA_POC_GPIO_H */

src/soc/amd/genoa_poc/include/soc/i2c.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_I2C_H
-#define AMD_GENOA_I2C_H
+#ifndef AMD_GENOA_POC_I2C_H
+#define AMD_GENOA_POC_I2C_H
 
 #include <gpio.h>
 #include <types.h>
@@ -33,4 +33,4 @@
 
 void reset_i2c_peripherals(void);
 
-#endif /* AMD_GENOA_I2C_H */
+#endif /* AMD_GENOA_POC_I2C_H */

src/soc/amd/genoa_poc/include/soc/iomap.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_IOMAP_H
-#define AMD_GENOA_IOMAP_H
+#ifndef AMD_GENOA_POC_IOMAP_H
+#define AMD_GENOA_POC_IOMAP_H
 
 #define I2C_MASTER_DEV_COUNT		6
 #define I2C_PERIPHERAL_DEV_COUNT	0
@@ -34,4 +34,4 @@
 #define APU_I3C2_BASE			0xfedd4000
 #define APU_I3C3_BASE			0xfedd6000
 
-#endif /* AMD_GENOA_IOMAP_H */
+#endif /* AMD_GENOA_POC_IOMAP_H */

src/soc/amd/genoa_poc/include/soc/lpc.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_LPC_H
-#define AMD_GENOA_LPC_H
+#ifndef AMD_GENOA_POC_LPC_H
+#define AMD_GENOA_POC_LPC_H
 
 #define SPI_BASE_ADDRESS_REGISTER	0xa0
 #define   SPI_BASE_ALIGNMENT		BIT(8)
@@ -13,4 +13,4 @@
 #define   SPI_ROM_ALT_ENABLE		BIT(0)
 #define   SPI_PRESERVE_BITS		(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))
 
-#endif /* AMD_GENOA_LPC_H */
+#endif /* AMD_GENOA_POC_LPC_H */

src/soc/amd/genoa_poc/include/soc/msr.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_MSR_H
-#define AMD_GENOA_MSR_H
+#ifndef AMD_GENOA_POC_MSR_H
+#define AMD_GENOA_POC_MSR_H
 
 /* MSRC001_00[6B:64] P-state [7:0] bit definitions */
 union pstate_msr {
@@ -38,4 +38,4 @@ union pstate_msr {
 #define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe7
 #define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe8
 
-#endif /* AMD_GENOA_MSR_H */
+#endif /* AMD_GENOA_POC_MSR_H */

src/soc/amd/genoa_poc/include/soc/nvs.h

@@ -4,12 +4,12 @@
 
 /*
  * NOTE: The layout of the global_nvs structure below must match the layout
- * in soc/soc/amd/genoa/acpi/globalnvs.asl !!!
+ * in soc/soc/amd/genoa_poc/acpi/globalnvs.asl !!!
  *
  */
 
-#ifndef AMD_GENOA_NVS_H
-#define AMD_GENOA_NVS_H
+#ifndef AMD_GENOA_POC_NVS_H
+#define AMD_GENOA_POC_NVS_H
 
 #include <stdint.h>
 
@@ -19,4 +19,4 @@ struct __packed global_nvs {
 	uint64_t	gpei; /* 0x08 - 0x0f - GPE Wake Source */
 };
 
-#endif /* AMD_GENOA_NVS_H */
+#endif /* AMD_GENOA_POC_NVS_H */

src/soc/amd/genoa_poc/include/soc/pci_devs.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_PCI_DEVS_H
-#define AMD_GENOA_PCI_DEVS_H
+#ifndef AMD_GENOA_POC_PCI_DEVS_H
+#define AMD_GENOA_POC_PCI_DEVS_H
 
 #include <device/pci_def.h>
 #include <amdblocks/pci_devs.h>
@@ -45,4 +45,4 @@
 #define DF_F7_DEVFN		PCI_DEVFN(DF_DEV, 7)
 #define SOC_DF_F7_DEV		_SOC_DEV(DF_DEV, 7)
 
-#endif
+#endif /* AMD_GENOA_POC_PCI_DEVS_H */

src/soc/amd/genoa_poc/include/soc/smi.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#ifndef AMD_GENOA_SMI_H
-#define AMD_GENOA_SMI_H
+#ifndef AMD_GENOA_POC_SMI_H
+#define AMD_GENOA_POC_SMI_H
 
 #include <types.h>
 
@@ -179,4 +179,4 @@
 
 #define SMI_MODE_MASK			0x03
 
-#endif /* AMD_GENOA_SMI_H */
+#endif /* AMD_GENOA_POC_SMI_H */

src/soc/amd/genoa_poc/include/soc/smu.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_SMU_H
-#define AMD_GENOA_SMU_H
+#ifndef AMD_GENOA_POC_SMU_H
+#define AMD_GENOA_POC_SMU_H
 
 /* SMU mailbox register offsets in SMN */
 #define SMN_SMU_MESG_ID		0x3b10530
@@ -20,4 +20,4 @@ enum smu_message_id {
  */
 void smu_sx_entry(void);
 
-#endif /* AMD_GENOA_SMU_H */
+#endif /* AMD_GENOA_POC_SMU_H */

src/soc/amd/genoa_poc/include/soc/soc_chip.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_GENOA_POC_SOC_CHIP_H_
+#define _SOC_GENOA_POC_SOC_CHIP_H_
+
+#include "../../chip.h"
+
+#endif /* _SOC_GENOA_POC_SOC_CHIP_H_ */

src/soc/amd/genoa_poc/include/soc/southbridge.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_SOUTHBRIDGE_H
-#define AMD_GENOA_SOUTHBRIDGE_H
+#ifndef AMD_GENOA_POC_SOUTHBRIDGE_H
+#define AMD_GENOA_POC_SOUTHBRIDGE_H
 
 #include <soc/iomap.h>
 
@@ -118,4 +118,4 @@
 void fch_pre_init(void);
 void fch_early_init(void);
 
-#endif /* AMD_GENOA_SOUTHBRIDGE_H */
+#endif /* AMD_GENOA_POC_SOUTHBRIDGE_H */

src/soc/amd/genoa_poc/include/soc/uart.h

@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_GENOA_UART_H
-#define AMD_GENOA_UART_H
+#ifndef AMD_GENOA_POC_UART_H
+#define AMD_GENOA_POC_UART_H
 
 #include <types.h>
 
 void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */
 
-#endif /* AMD_GENOA_UART_H */
+#endif /* AMD_GENOA_POC_UART_H */

src/vendorcode/amd/opensil/genoa_poc/ramstage.c

@@ -66,7 +66,7 @@ static void setup_rc_manager_default(void)
 #define NUM_XHCI_CONTROLLERS 2
 static void configure_usb(void)
 {
-	const struct soc_amd_genoa_config *soc_config = config_of_soc();
+	const struct soc_amd_genoa_poc_config *soc_config = config_of_soc();
 	const struct soc_usb_config *usb = &soc_config->usb;
 
 	FCHUSB_INPUT_BLK *fch_usb_data = SilFindStructure(SilId_FchUsb, 0);