tegra132/pistachio: Increase romstage size in memlayout.ld
These SoCs have come within a kilobyte of their romstage limit, so let's expand that a little to make room for future core code contributions. (In the Tegra case just by copying the layout from Tegra210, because why not? Keeps things simple.) BRANCH=None BUG=None TEST=Ran abuild with and without --chromeos for Foster, Rush, Ryu, Smaug and Urara. Change-Id: If8c1ea81cf9827412c78d67a09d54e7a2dc044ac Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13668 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -36,9 +36,9 @@ SECTIONS
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* and then through the identity mapping in ROM stage.
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* and then through the identity mapping in ROM stage.
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*/
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*/
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SRAM_START(0x1a000000)
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SRAM_START(0x1a000000)
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ROMSTAGE(0x1a005000, 40K)
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ROMSTAGE(0x1a005000, 60K)
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VBOOT2_WORK(0x1a00f000, 12K)
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VBOOT2_WORK(0x1a014000, 12K)
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PRERAM_CBFS_CACHE(0x1a012000, 56K)
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PRERAM_CBFS_CACHE(0x1a017000, 56K)
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SRAM_END(0x1a066000)
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SRAM_END(0x1a066000)
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/* Bootblock executes out of KSEG0 and sets up the identity mapping.
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/* Bootblock executes out of KSEG0 and sets up the identity mapping.
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@ -29,17 +29,17 @@ SECTIONS
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{
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{
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SRAM_START(0x40000000)
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SRAM_START(0x40000000)
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PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
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PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
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PRERAM_CBFS_CACHE(0x40002000, 72K)
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PRERAM_CBFS_CACHE(0x40002000, 36K)
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VBOOT2_WORK(0x40014000, 12K)
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VBOOT2_WORK(0x4000B000, 12K)
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#if ENV_ARM64
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#if ENV_ARM64
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STACK(0x40017000, 3K)
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STACK(0x4000E000, 3K)
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#else /* AVP gets a separate stack to avoid any chance of handoff races. */
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#else /* AVP gets a separate stack to avoid any chance of handoff races. */
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STACK(0x40017C00, 3K)
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STACK(0x4000EC00, 3K)
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#endif
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#endif
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TIMESTAMP(0x40018800, 2K)
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TIMESTAMP(0x4000F800, 2K)
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BOOTBLOCK(0x40019000, 22K)
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BOOTBLOCK(0x40010000, 28K)
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VERSTAGE(0x4001e800, 55K)
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VERSTAGE(0x40017000, 64K)
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ROMSTAGE(0x4002c400, 77K)
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ROMSTAGE(0x40027000, 100K)
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SRAM_END(0x40040000)
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SRAM_END(0x40040000)
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DRAM_START(0x80000000)
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DRAM_START(0x80000000)
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