soc/intel/icelake: Make use of common thermal code for ICL
This patch ports CB:34522 and CB:33147 changes from CNL to ICL. TEST=Build and boot dragonegg Change-Id: I0b983005f16fe182e634eac63fef4f6b22197a85 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34649 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -148,6 +148,7 @@ chip soc/intel/icelake
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#| | required to set up a BAR |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | for TPM communication |
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#| | before memory is up |
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#| | before memory is up |
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#| pch_thermal_trip | PCH Trip Temperature |
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#+-------------------+---------------------------+
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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register "common_soc_config" = "{
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@ -165,6 +166,7 @@ chip soc/intel/icelake
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.sda_hold = 36,
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.sda_hold = 36,
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}
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}
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},
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},
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.pch_thermal_trip = 77,
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}"
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}"
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# GPIO PM programming
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# GPIO PM programming
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@ -181,7 +183,7 @@ chip soc/intel/icelake
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device pci 00.0 on end # Host Bridge
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 off end # SA Thermal device
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device pci 04.0 off end # SA Thermal device
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device pci 12.0 off end # Thermal Subsystem
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device pci 12.0 on end # Thermal Subsystem
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device pci 12.5 off end # UFS SCS
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device pci 12.5 off end # UFS SCS
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device pci 12.6 off end # GSPI #2
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device pci 12.6 off end # GSPI #2
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device pci 14.0 on
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device pci 14.0 on
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@ -51,6 +51,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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select SOC_INTEL_COMMON_BLOCK_THERMAL
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_COMMON_RESET
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select SSE2
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select SSE2
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@ -23,6 +23,7 @@
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/tco.h>
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#include <intelblocks/tco.h>
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#include <intelblocks/thermal.h>
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#include <reg_script.h>
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#include <reg_script.h>
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#include <spi-generic.h>
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#include <spi-generic.h>
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#include <soc/p2sb.h>
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#include <soc/p2sb.h>
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@ -62,6 +63,15 @@ static void pch_finalize(void)
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/* TCO Lock down */
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/* TCO Lock down */
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tco_lockdown();
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tco_lockdown();
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/*
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* Set low maximum temp threshold value used for dynamic thermal sensor
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* shutdown consideration.
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*
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* If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
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* thermal sensor when CPU is in a C-state and DTS Temp <= LTT.
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*/
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pch_thermal_configuration();
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/*
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/*
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* Disable ACPI PM timer based on dt policy
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* Disable ACPI PM timer based on dt policy
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*
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*
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