soc/intel: Rename pcr.asl to pch_pcr.asl

The PCR (Private Configuration Register) is applicable to access the
P2SB register space starting with the Intel SkyLake generation of SoC.

Prior to Intel Meteor Lake SoC generation, the only P2SB existed inside
the PCH die. Starting with Meteor Lake SoC, there are two P2SB, one in
SoC die (same as PCH die for U/H SoC) and another in IOE die.

This patch renames pcr.asl to pch_pcr.asl to reflect the actual source
of the P2SB IP in the die (i.e., SoC die or PCH die).

BUG=b:290856936
TEST=Able to build and boot google/rex.

Change-Id: Idb66293eaab01e1d4bcd4e9482157575fb0adf04
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76407
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

src/soc/intel/alderlake/acpi/southbridge.asl

@@ -6,7 +6,7 @@
 #include <soc/pcr_ids.h>
 
 /* PCR access */
-#include <soc/intel/common/acpi/pcr.asl>
+#include <soc/intel/common/acpi/pch_pcr.asl>
 
 /* PCH clock */
 #include "camera_clock_ctl.asl"

src/soc/intel/cannonlake/acpi/southbridge.asl

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 /* PCR access */
-#include <soc/intel/common/acpi/pcr.asl>
+#include <soc/intel/common/acpi/pch_pcr.asl>
 
 /* eMMC, SD Card */
 #include "scs.asl"

src/soc/intel/elkhartlake/acpi/southbridge.asl

@@ -9,7 +9,7 @@
 #include "pci_irqs.asl"
 
 /* PCR access */
-#include <soc/intel/common/acpi/pcr.asl>
+#include <soc/intel/common/acpi/pch_pcr.asl>
 
 /* GPIO controller */
 #include "gpio.asl"

src/soc/intel/jasperlake/acpi/southbridge.asl

@@ -9,7 +9,7 @@
 #include "pci_irqs.asl"
 
 /* PCR access */
-#include <soc/intel/common/acpi/pcr.asl>
+#include <soc/intel/common/acpi/pch_pcr.asl>
 
 /* PCH clock */
 #include "camera_clock_ctl.asl"

src/soc/intel/meteorlake/acpi/southbridge.asl

@@ -6,7 +6,7 @@
 #include <soc/pcr_ids.h>
 
 /* PCR access */
-#include <soc/intel/common/acpi/pcr.asl>
+#include <soc/intel/common/acpi/pch_pcr.asl>
 
 /* PCH clock */
 #include "camera_clock_ctl.asl"

src/soc/intel/skylake/acpi/pch.asl

@@ -27,7 +27,7 @@
 #include "pcie.asl"
 
 /* PCR Access */
-#include <soc/intel/common/acpi/pcr.asl>
+#include <soc/intel/common/acpi/pch_pcr.asl>
 
 /* PMC 0:1f.2 */
 #include "pmc.asl"

src/soc/intel/tigerlake/acpi/southbridge.asl

@@ -6,7 +6,7 @@
 #include <soc/pcr_ids.h>
 
 /* PCR access */
-#include <soc/intel/common/acpi/pcr.asl>
+#include <soc/intel/common/acpi/pch_pcr.asl>
 
 /* PCH clock */
 #include "camera_clock_ctl.asl"

src/soc/intel/xeon_sp/acpi/gpio.asl

@@ -4,7 +4,7 @@
 #include <soc/pcr_ids.h>
 #include <soc/irq.h>
 #include <soc/intel/common/block/acpi/acpi/gpio_op.asl>
-#include <soc/intel/common/acpi/pcr.asl>
+#include <soc/intel/common/acpi/pch_pcr.asl>
 
 Device (GPIO)
 {