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soc/amd/stoneyridge: clean up OSCOUT1_ClkOutputEnb 

Change OSCOUT1_ClkOutputEnb programming to use registers from iomap.h
and southbridge.h

BUG=b:69220826
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt

Change-Id: Ib138dae6057394740c415e882e4dbd925882c2de
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This commit is contained in:
Garrett Kirkendall 2018-03-06 09:05:20 -06:00 committed by Martin Roth
parent 050b6fb125
commit d255830418
2 changed files with 7 additions and 4 deletions
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3
src/soc/amd/stoneyridge/include/soc/southbridge.h
View File

@ -247,7 +247,8 @@
#define SPI100_HOST_PREF_CONFIG 0x2c #define SPI100_HOST_PREF_CONFIG 0x2c
#define SPI_RD4DW_EN_HOST BIT(15) #define SPI_RD4DW_EN_HOST BIT(15)
#define FCH_MISC_REG40_OSCOUT1_EN BIT(2) #define MISC_MISC_CLK_CNTL_1 0x40
#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */
/* IO 0xcf9 - Reset control port*/ /* IO 0xcf9 - Reset control port*/
#define FULL_RST BIT(3) #define FULL_RST BIT(3)

8
src/soc/amd/stoneyridge/southbridge.c
View File

@ -360,16 +360,18 @@ void sb_lpc_decode(void)
void sb_clk_output_48Mhz(void) void sb_clk_output_48Mhz(void)
{ {
u32 ctrl; u32 ctrl;
u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(MISC_MMIO_BASE
+ MISC_MISC_CLK_CNTL_1);
/* /*
* Enable the X14M_25M_48M_OSC pin and leaving it at it's default so * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so
* 48Mhz will be on ball AP13 (FT3b package) * 48Mhz will be on ball AP13 (FT3b package)
*/ */
ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40)); ctrl = read32(misc_clk_cntl_1_ptr);
/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
ctrl &= ~FCH_MISC_REG40_OSCOUT1_EN; ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB;
write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); write32(misc_clk_cntl_1_ptr, ctrl);
} }
static uintptr_t sb_spibase(void) static uintptr_t sb_spibase(void)