soc/intel/xeon_sp/cpx: add VT-d support
Intel CPX-SP FSP added support for VT-d through adding UPD parameter X2apic. Based on devicetree.cb setting, enable VT-d programming through FSP-M. When VT-d is enabled, add DMAR ACPI table. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ic66374af6e53fb847c1bdc324eb3f4e01c334a94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This commit is contained in:
Jonathan Zhang
Angel Pons
parent
056f81988f
commit
d2718c9381
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@ -448,12 +448,315 @@ static unsigned long acpi_fill_slit(unsigned long current)
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return current;
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}
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/*
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* Ports Stack Stack(HOB) IioConfigIou
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* ==========================================
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* 0 CSTACK stack 0 IOU0
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* 1A..1D PSTACK0 stack 1 IOU1
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* 2A..2D PSTACK1 stack 2 IOU2
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* 3A..3D PSTACK2 stack 4 IOU3
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*/
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static int get_stack_for_port(int p)
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{
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if (p == 0)
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return CSTACK;
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else if (p >= PORT_1A && p <= PORT_1D)
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return PSTACK0;
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else if (p >= PORT_2A && p <= PORT_2D)
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return PSTACK1;
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else //if (p >= PORT_3A && p <= PORT_3D)
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return PSTACK2;
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}
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static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack)
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{
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int IoApicID[] = {
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// socket 0
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PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID,
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PC04_IOAPIC_ID, PC05_IOAPIC_ID,
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// socket 1
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PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID,
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PC10_IOAPIC_ID, PC11_IOAPIC_ID,
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};
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uint32_t enum_id;
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unsigned long tmp = current;
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size_t hob_size;
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const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
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const IIO_UDS *hob = fsp_find_extension_hob_by_guid(
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fsp_hob_iio_universal_data_guid, &hob_size);
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assert(hob != NULL && hob_size != 0);
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uint32_t bus = hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase;
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uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment;
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uint32_t reg_base =
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hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress;
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printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n",
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__func__, socket, stack, bus, pcie_seg, reg_base);
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// Add DRHD Hardware Unit
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if (socket == 0 && stack == CSTACK) {
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printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, "
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"Register Base Address: 0x%x\n",
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DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base);
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current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL,
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pcie_seg, reg_base);
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} else {
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printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, "
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"Register Base Address: 0x%x\n", 0, pcie_seg, reg_base);
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current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base);
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}
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// Add PCH IOAPIC
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if (socket == 0 && stack == CSTACK) {
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printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, "
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"PCI Path: 0x%x, 0x%x\n",
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PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER,
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PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM);
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current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID,
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PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM);
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}
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// Add IOAPIC entry
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enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack];
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printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, "
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"PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM);
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current += acpi_create_dmar_ds_ioapic(current, enum_id, bus,
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APIC_DEV_NUM, APIC_FUNC_NUM);
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// Add CBDMA devices for CSTACK
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if (socket != 0 && stack == CSTACK) {
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for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) {
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printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, "
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"PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n",
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0, bus, CBDMA_DEV_NUM, cbdma_func_id);
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current += acpi_create_dmar_ds_pci(current,
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bus, CBDMA_DEV_NUM, cbdma_func_id);
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}
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}
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// Add PCIe Ports
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if (socket != 0 || stack != CSTACK) {
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IIO_RESOURCE_INSTANCE iio_resource =
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hob->PlatformData.IIO_resource[socket];
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for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) {
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if (get_stack_for_port(p) != stack)
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continue;
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uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device;
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uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function;
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uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func),
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PCI_VENDOR_ID);
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if (id == 0xffffffff)
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continue;
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printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, "
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"PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n",
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0, bus, dev, func);
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current += acpi_create_dmar_ds_pci_br(current,
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bus, dev, func);
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}
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// Add VMD
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if (hob->PlatformData.VMDStackEnable[socket][stack] &&
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stack >= PSTACK0 && stack <= PSTACK2) {
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printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, "
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"PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n",
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0, bus, VMD_DEV_NUM, VMD_FUNC_NUM);
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current += acpi_create_dmar_ds_pci(current,
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bus, VMD_DEV_NUM, VMD_FUNC_NUM);
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}
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}
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// Add HPET
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if (socket == 0 && stack == CSTACK) {
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uint16_t hpet_capid = read16((void *)HPET_BASE_ADDRESS);
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uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count
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printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n",
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__func__, hpet_capid, num_hpets);
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//BIT 15
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if (num_hpets && (num_hpets != 0x1f) &&
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(read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) {
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printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, "
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"PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n",
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0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM);
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current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM,
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HPET_DEV_NUM, HPET0_FUNC_NUM);
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}
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}
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acpi_dmar_drhd_fixup(tmp, current);
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return current;
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}
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static unsigned long acpi_create_atsr(unsigned long current)
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{
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size_t hob_size;
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const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
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const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size);
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assert(hob != NULL && hob_size != 0);
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for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) {
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uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment;
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unsigned long tmp = current;
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bool first = true;
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IIO_RESOURCE_INSTANCE iio_resource =
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hob->PlatformData.IIO_resource[socket];
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for (int stack = 0; stack <= PSTACK2; ++stack) {
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uint32_t bus = iio_resource.StackRes[stack].BusBase;
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uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress;
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if (!vtd_base)
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continue;
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uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW));
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printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, "
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"vtd_mmio_cap: 0x%llx\n",
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__func__, socket, stack, bus, vtd_base, vtd_mmio_cap);
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// ATSR is applicable only for platform supporting device IOTLBs
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// through the VT-d extended capability register
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assert(vtd_mmio_cap != 0xffffffffffffffff);
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if ((vtd_mmio_cap & 0x4) == 0) // BIT 2
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continue;
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for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) {
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if (socket == 0 && p == 0)
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continue;
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if (get_stack_for_port(p) != stack)
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continue;
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uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device;
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uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function;
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u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func),
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PCI_VENDOR_ID);
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if (id == 0xffffffff)
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continue;
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if (first) {
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printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, "
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"PCI Segment Number: 0x%x\n",
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0, pcie_seg);
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current += acpi_create_dmar_atsr(current, 0, pcie_seg);
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first = 0;
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}
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printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, "
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"PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n",
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0, bus, dev, func);
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current += acpi_create_dmar_ds_pci_br(current, bus, dev, func);
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}
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}
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if (tmp != current)
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acpi_dmar_atsr_fixup(tmp, current);
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}
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return current;
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}
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static unsigned long acpi_create_rmrr(unsigned long current)
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{
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uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000);
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uint32_t *ptr;
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// reserve memory
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ptr = cbmem_find(CBMEM_ID_STORAGE_DATA);
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if (!ptr) {
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ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size);
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assert(ptr != NULL);
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memset(ptr, 0, size);
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}
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unsigned long tmp = current;
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printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, "
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"End Address (limit): 0x%x\n",
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0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1));
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current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr,
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(uint32_t) ((uint32_t) ptr + size - 1));
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printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, "
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"PCI Path: 0x%x, 0x%x\n",
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0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM);
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current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER,
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PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM);
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acpi_dmar_rmrr_fixup(tmp, current);
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return current;
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}
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static unsigned long acpi_create_rhsa(unsigned long current)
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{
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size_t hob_size;
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const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
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const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size);
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assert(hob != NULL && hob_size != 0);
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for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) {
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IIO_RESOURCE_INSTANCE iio_resource =
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hob->PlatformData.IIO_resource[socket];
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for (int stack = 0; stack <= PSTACK2; ++stack) {
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uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress;
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if (!vtd_base)
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continue;
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printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, "
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"Proximity Domain: 0x%x\n", vtd_base, socket);
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current += acpi_create_dmar_rhsa(current, vtd_base, socket);
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}
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}
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return current;
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}
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static unsigned long acpi_fill_dmar(unsigned long current)
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{
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size_t hob_size;
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const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
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const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size);
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assert(hob != NULL && hob_size != 0);
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// DRHD
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for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) {
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int socket = iio;
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if (socket == hob->PlatformData.numofIIO) // socket 0 should be last DRHD entry
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socket = 0;
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if (socket == 0) {
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for (int stack = 1; stack <= PSTACK2; ++stack)
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current = acpi_create_drhd(current, socket, stack);
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current = acpi_create_drhd(current, socket, CSTACK);
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} else {
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for (int stack = 0; stack <= PSTACK2; ++stack)
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current = acpi_create_drhd(current, socket, stack);
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}
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}
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// RMRR
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current = acpi_create_rmrr(current);
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// ATSR - causes hang
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current = acpi_create_atsr(current);
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// RHSA
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current = acpi_create_rhsa(current);
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return current;
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}
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unsigned long northbridge_write_acpi_tables(const struct device *device,
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unsigned long current,
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struct acpi_rsdp *rsdp)
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{
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acpi_srat_t *srat;
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acpi_slit_t *slit;
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acpi_dmar_t *dmar;
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const struct soc_intel_xeon_sp_cpx_config *const config = config_of(device);
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/* SRAT */
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current = ALIGN(current, 8);
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@ -471,5 +774,18 @@ unsigned long northbridge_write_acpi_tables(const struct device *device,
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current += slit->header.length;
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acpi_add_table(rsdp, slit);
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/* DMAR */
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if (config->vtd_support) {
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current = ALIGN(current, 8);
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dmar = (acpi_dmar_t *)current;
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printk(BIOS_DEBUG, "ACPI: * DMAR\n");
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printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n",
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(DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT));
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acpi_create_dmar(dmar, (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT), acpi_fill_dmar);
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current += dmar->header.length;
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current = acpi_align_current(current);
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acpi_add_table(rsdp, dmar);
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}
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return current;
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}
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@ -84,6 +84,9 @@ struct soc_intel_xeon_sp_cpx_config {
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uint32_t pstate_req_ratio;
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uint8_t vtd_support;
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uint8_t x2apic;
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/* Generic IO decode ranges */
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uint32_t gen1_dec;
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uint32_t gen2_dec;
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@ -15,6 +15,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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{
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FSPM_CONFIG *m_cfg = &mupd->FspmConfig;
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const struct device *dev;
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const config_t *config = config_of_soc();
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/* ErrorLevel - 0 (disable) to 8 (verbose) */
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m_cfg->DebugPrintLevel = 8;
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@ -68,5 +69,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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dev = pcidev_path_on_root(PCH_DEVFN_THERMAL);
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m_cfg->ThermalDeviceEnable = dev && dev->enabled;
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/* Enable VT-d according to DTB */
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m_cfg->VtdSupport = config->vtd_support;
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m_cfg->X2apic = config->x2apic;
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mainboard_memory_init_params(mupd);
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}
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