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mb/google/brya/var/gimble: Configure GPIO to release PERST# earlier 

This change in power sequencing appears to fix issues with power
consumption of the SD card controller. Possibly this change
ensures the device has enough time to properly initialize itself
after reset is deasserted but before it is accessed.

BUG=b:206014046
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I90e5dd074ceda365283fe7e1f43dfd8c692d7338
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Mark Hsieh 2021-12-21 21:04:12 +08:00 committed by Tim Wawrzynczak
parent baf027d50c
commit d27dd97e17
2 changed files with 10 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/brya/variants/gimble/gpio.c
View File

@ -83,6 +83,8 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_H8, NONE), PAD_NC(GPP_H8, NONE),
/* H9 : I2C4_SCL ==> NC */ /* H9 : I2C4_SCL ==> NC */
PAD_NC(GPP_H9, NONE), PAD_NC(GPP_H9, NONE),
/* H13 : I2C7_SCL ==> EN_PP3300_SD */
PAD_CFG_GPO(GPP_H13, 1, DEEP),
/* H15 : DDPB_CTRLCLK ==> NC */ /* H15 : DDPB_CTRLCLK ==> NC */
PAD_NC(GPP_H15, NONE), PAD_NC(GPP_H15, NONE),
/* H17 : DDPB_CTRLDATA ==> NC*/ /* H17 : DDPB_CTRLDATA ==> NC*/
@ -149,12 +151,14 @@ static const struct pad_config early_gpio_table[] = {
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/* H13 : I2C7_SCL ==> EN_PP3300_SD */ /* H13 : I2C7_SCL ==> EN_PP3300_SD */
PAD_NC(GPP_H13, UP_20K), PAD_CFG_GPO(GPP_H13, 1, DEEP),
}; };
static const struct pad_config romstage_gpio_table[] = { static const struct pad_config romstage_gpio_table[] = {
/* B4 : PROC_GP3 ==> SSD_PERST_L */ /* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 1, DEEP), PAD_CFG_GPO(GPP_B4, 1, DEEP),
/* D18 : UART1_TXD ==> SD_PE_RST_L */
PAD_CFG_GPO(GPP_D18, 1, DEEP),
}; };
const struct pad_config *variant_gpio_override_table(size_t *num) const struct pad_config *variant_gpio_override_table(size_t *num)

6
src/mainboard/google/brya/variants/gimble4es/gpio.c
View File

@ -83,6 +83,8 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_H8, NONE), PAD_NC(GPP_H8, NONE),
/* H9 : I2C4_SCL ==> NC */ /* H9 : I2C4_SCL ==> NC */
PAD_NC(GPP_H9, NONE), PAD_NC(GPP_H9, NONE),
/* H13 : I2C7_SCL ==> EN_PP3300_SD */
PAD_CFG_GPO(GPP_H13, 1, DEEP),
/* H15 : DDPB_CTRLCLK ==> NC */ /* H15 : DDPB_CTRLCLK ==> NC */
PAD_NC(GPP_H15, NONE), PAD_NC(GPP_H15, NONE),
/* H17 : DDPB_CTRLDATA ==> NC*/ /* H17 : DDPB_CTRLDATA ==> NC*/
@ -149,12 +151,14 @@ static const struct pad_config early_gpio_table[] = {
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/* H13 : I2C7_SCL ==> EN_PP3300_SD */ /* H13 : I2C7_SCL ==> EN_PP3300_SD */
PAD_NC(GPP_H13, UP_20K), PAD_CFG_GPO(GPP_H13, 1, DEEP),
}; };
static const struct pad_config romstage_gpio_table[] = { static const struct pad_config romstage_gpio_table[] = {
/* B4 : PROC_GP3 ==> SSD_PERST_L */ /* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 1, DEEP), PAD_CFG_GPO(GPP_B4, 1, DEEP),
/* D18 : UART1_TXD ==> SD_PE_RST_L */
PAD_CFG_GPO(GPP_D18, 1, DEEP),
}; };
const struct pad_config *variant_gpio_override_table(size_t *num) const struct pad_config *variant_gpio_override_table(size_t *num)