- A new test case for romcc
- Minor romcc fixes - In smbus_wail_until_done a romcc glitch with || in romcc where it likes to run out of registers. Use | to be explicit that I don't need the short circuiting behavior. - Remove unused #defines from coherent_ht.c - Update the test in auto.c to 512M - Add definition of log2 to romcc_io.h - Implement SPD memory sizing in raminit.c - Reduce the number of memory devices back 2 to for the SOLO board. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
99acb49cf7
commit
d3283ec05f
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@ -35,6 +35,18 @@ static void hlt(void)
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__builtin_hlt();
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}
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int log2(int value)
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{
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/* __builtin_bsr is a exactly equivalent to the x86 machine
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* instruction with the exception that it returns -1
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* when the value presented to it is zero.
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* Otherwise __builtin_bsr returns the zero based index of
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* the highest bit set.
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*/
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return __builtin_bsr(value);
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}
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typedef __builtin_msr_t msr_t;
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static msr_t rdmsr(unsigned long index)
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@ -11,6 +11,13 @@
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#define NODE_ID 0x60
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#define HT_INIT_CONTROL 0x6c
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#define HTIC_ColdR_Detect (1<<4)
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#define HTIC_BIOSR_Detect (1<<5)
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#define HTIC_INIT_Detect (1<<6)
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static int boot_cpu(void)
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{
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volatile unsigned long *local_apic;
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@ -59,6 +66,16 @@ static int cpu_init_detected(void)
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}
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static void print_debug_pci_dev(unsigned dev)
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{
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print_debug("PCI: ");
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print_debug_hex8((dev >> 16) & 0xff);
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print_debug_char(':');
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print_debug_hex8((dev >> 11) & 0x1f);
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print_debug_char('.');
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print_debug_hex8((dev >> 8) & 7);
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}
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static void print_pci_devices(void)
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{
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device_t dev;
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@ -72,15 +89,33 @@ static void print_pci_devices(void)
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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print_debug("PCI: 00:");
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print_debug_hex8(dev >> 11);
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print_debug_char('.');
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print_debug_hex8((dev >> 8) & 7);
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print_debug_pci_dev(dev);
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print_debug("\r\n");
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}
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}
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static void dump_pci_device(unsigned dev)
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{
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int i;
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print_debug_pci_dev(dev);
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print_debug("\r\n");
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for(i = 0; i <= 255; i++) {
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unsigned char val;
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if ((i & 0x0f) == 0) {
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print_debug_hex8(i);
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print_debug_char(':');
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}
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val = pci_read_config8(dev, i);
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print_debug_char(' ');
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print_debug_hex8(val);
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if ((i & 0x0f) == 0x0f) {
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print_debug("\r\n");
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}
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}
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}
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static void dump_spd_registers(void)
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{
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unsigned device;
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@ -112,6 +147,7 @@ static void dump_spd_registers(void)
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}
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}
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static void main(void)
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{
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uart_init();
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@ -132,7 +168,16 @@ static void main(void)
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sdram_initialize();
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dump_spd_registers();
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/* Check the first 8M */
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ram_check(0x00100000, 0x00800000);
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dump_pci_device(PCI_DEV(0, 0x18, 2));
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/* Check the first 512M */
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msr_t msr;
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msr = rdmsr(TOP_MEM);
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print_debug("TOP_MEM: ");
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print_debug_hex32(msr.hi);
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print_debug_hex32(msr.lo);
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print_debug("\r\n");
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#warning "FIXME if I pass msr.lo somehow I get the value 0x00000030 as stop in ram_check"
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ram_check(0x00000000, 0x20000000);
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}
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}
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@ -1,11 +1,3 @@
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#define COHERENT_AMD_SOLO 1 /* AMD Solo motherboard */
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#define COHERENT_ARIMA_HDAMA 2 /* Arima HDAMA motherboard */
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#ifndef COHERENT_CONFIG
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#define COHERENT_CONFIG COHERENT_AMD_SOLO
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#endif
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static void setup_coherent_ht_domain(void)
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{
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static const unsigned int register_values[] = {
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@ -1,3 +1,4 @@
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#include <cpu/k8/mtrr.h>
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#define MEMORY_SUSE_SOLO 1 /* SuSE Solo configuration */
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#define MEMORY_LNXI_SOLO 2 /* LNXI Solo configuration */
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#define MEMORY_LNXI_HDAMA 3 /* LNXI HDAMA configuration */
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@ -1112,6 +1113,192 @@ static void sdram_set_registers(void)
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print_debug("done.\r\n");
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}
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struct dimm_size {
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unsigned long side1;
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unsigned long side2;
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};
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static struct dimm_size spd_get_dimm_size(unsigned device)
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{
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/* Calculate the log base 2 size of a DIMM in bits */
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struct dimm_size sz;
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int value, low;
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sz.side1 = 0;
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sz.side2 = 0;
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/* Note it might be easier to use byte 31 here, it has the DIMM size as
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* a multiple of 4MB. The way we do it now we can size both
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* sides of an assymetric dimm.
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*/
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value = smbus_read_byte(device, 3); /* rows */
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if (value < 0) return sz;
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sz.side1 += value & 0xf;
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value = smbus_read_byte(device, 4); /* columns */
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if (value < 0) return sz;
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sz.side1 += value & 0xf;
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value = smbus_read_byte(device, 17); /* banks */
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if (value < 0) return sz;
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sz.side1 += log2(value & 0xff);
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/* Get the module data widht and convert it to a power of two */
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value = smbus_read_byte(device, 7); /* (high byte) */
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if (value < 0) return sz;
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value &= 0xff;
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value <<= 8;
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low = smbus_read_byte(device, 6); /* (low byte) */
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if (low < 0) return sz;
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value = value | (low & 0xff);
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sz.side1 += log2(value);
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/* side 2 */
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value = smbus_read_byte(device, 5); /* number of physical banks */
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if (value <= 1) return sz;
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/* Start with the symmetrical case */
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sz.side2 = sz.side1;
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value = smbus_read_byte(device, 3); /* rows */
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if (value < 0) return sz;
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if ((value & 0xf0) == 0) return sz; /* If symmetrical we are done */
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sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */
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sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */
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value = smbus_read_byte(device, 4); /* columns */
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if (value < 0) return sz;
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sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */
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sz.side2 += ((value >> 4) & 0x0f); /* Add in columsn on side 2 */
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return sz;
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}
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static unsigned spd_to_dimm_side0(unsigned device)
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{
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return (device - SMBUS_MEM_DEVICE_START) << 1;
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}
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static unsigned spd_to_dimm_side1(unsigned device)
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{
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return ((device - SMBUS_MEM_DEVICE_START) << 1) + 1;
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}
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static void set_dimm_size(unsigned long size, unsigned index)
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{
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unsigned value = 0;
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/* Make certain the dimm is at least 32MB */
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if (size >= (25 + 3)) {
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/* Place the dimm size in 32 MB quantities in the bits 31 - 21.
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* The initialize dimm size is in bits.
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* Set the base enable bit0.
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*/
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value = (1 << ((size - (25 + 3)) + 21)) | 1;
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}
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/* Set the appropriate DIMM base address register */
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pci_write_config32(PCI_DEV(0, 0x18, 2), 0x40 + (index << 2), value);
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}
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static void spd_set_ram_size(void)
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{
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unsigned device;
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for(device = SMBUS_MEM_DEVICE_START;
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device <= SMBUS_MEM_DEVICE_END;
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device += SMBUS_MEM_DEVICE_INC)
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{
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struct dimm_size sz;
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sz = spd_get_dimm_size(device);
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set_dimm_size(sz.side1, spd_to_dimm_side0(device));
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set_dimm_size(sz.side2, spd_to_dimm_side1(device));
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}
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}
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static void set_top_mem(unsigned tom_k)
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{
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/* Error if I don't have memory */
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if (!tom_k) {
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die("No memory");
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}
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/* Now set top of memory */
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msr_t msr;
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msr.lo = (tom_k & 0x003fffff) << 10;
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msr.hi = (tom_k & 0xffc00000) >> 22;
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wrmsr(TOP_MEM, msr);
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#if 1
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/* And report the amount of memory. (I run out of registers if i don't) */
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print_debug("RAM: 0x");
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print_debug_hex32(tom_k);
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print_debug(" KB\r\n");
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#endif
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}
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static void order_dimms(void)
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{
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unsigned long tom;
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unsigned mask;
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unsigned index;
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/* Remember which registers we have used in the high 8 bits of tom */
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tom = 0;
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for(;;) {
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/* Find the largest remaining canidate */
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unsigned canidate;
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uint32_t csbase, csmask;
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unsigned size;
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csbase = 0;
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canidate = 0;
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for(index = 0; index < 8; index++) {
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uint32_t value;
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value = pci_read_config32(PCI_DEV(0, 0x18, 2), 0x40 + (index << 2));
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/* Is it enabled? */
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if (!(value & 1)) {
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continue;
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}
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/* Is it greater? */
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if (value <= csbase) {
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continue;
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}
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/* Has it already been selected */
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if (tom & (1 << (index + 24))) {
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continue;
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}
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/* I have a new canidate */
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csbase = value;
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canidate = index;
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}
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/* See if I have found a new canidate */
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if (csbase == 0) {
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break;
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}
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/* Remember I have used this register */
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tom |= (1 << (canidate + 24));
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/* Remember the dimm size */
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size = csbase >> 21;
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/* Recompute the cs base register value */
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csbase = (tom << 21) | 1;
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/* Increment the top of memory */
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tom += size;
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/* Compute the memory mask */
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csmask = ((size -1) << 21);
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csmask |= 0xfe00; /* For now don't optimize */
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/* Write the new base register */
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pci_write_config32(PCI_DEV(0, 0x18, 2), 0x40 + (canidate << 2), csbase);
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pci_write_config32(PCI_DEV(0, 0x18, 2), 0x60 + (canidate << 2), csmask);
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}
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set_top_mem((tom & ~0xff000000) << 15);
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}
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#define DRAM_CONFIG_LOW 0x90
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#define DCL_DLL_Disable (1<<0)
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#define DCL_D_DRV (1<<1)
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@ -1122,20 +1309,21 @@ static void sdram_set_registers(void)
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#define DCL_MemClrStatus (1<<11)
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#define DCL_DimmEcEn (1<<17)
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#define NODE_ID 0x60
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#define HT_INIT_CONTROL 0x6c
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#define HTIC_ColdR_Detect (1<<4)
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#define HTIC_BIOSR_Detect (1<<5)
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#define HTIC_INIT_Detect (1<<6)
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static void sdram_set_spd_registers(void)
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static void spd_set_ecc_mode(void)
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{
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unsigned long dcl;
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dcl = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW);
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/* Until I know what is going on disable ECC support */
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dcl &= ~DCL_DimmEcEn;
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pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, dcl);
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}
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static void sdram_set_spd_registers(void)
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{
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spd_set_ram_size();
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spd_set_ecc_mode();
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order_dimms();
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}
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#define TIMEOUT_LOOPS 300000
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|
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@ -53,7 +53,7 @@ static int smbus_wait_until_done(void)
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smbus_delay();
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val = inw(SMBUS_IO_BASE + SMBGSTATUS);
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if (((val & 0x8) == 0) || ((val & 0x437) != 0)) {
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if (((val & 0x8) == 0) | ((val & 0x437) != 0)) {
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break;
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}
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} while(--loops);
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|
|
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@ -51,6 +51,7 @@ TESTS=\
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simple_test30.c \
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simple_test31.c \
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simple_test32.c \
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simple_test33.c \
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raminit_test.c \
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raminit_test2.c \
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raminit_test3.c \
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|
|
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|
@ -1428,6 +1428,10 @@ static struct triple *pre_triple(struct compile_state *state,
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{
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struct block *block;
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struct triple *ret;
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/* If I am an OP_PIECE jump to the real instruction */
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if (base->op == OP_PIECE) {
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base = MISC(base, 0);
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}
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block = block_of_triple(state, base);
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ret = build_triple(state, op, type, left, right,
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base->filename, base->line, base->col);
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|
|
@ -1447,6 +1451,17 @@ static struct triple *post_triple(struct compile_state *state,
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{
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struct block *block;
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struct triple *ret;
|
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int zlhs;
|
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/* If I am an OP_PIECE jump to the real instruction */
|
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if (base->op == OP_PIECE) {
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base = MISC(base, 0);
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}
|
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/* If I have a left hand side skip over it */
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zlhs = TRIPLE_LHS(base->sizes);
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if (zlhs && (base->op != OP_WRITE) && (base->op != OP_STORE)) {
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base = LHS(base, zlhs - 1);
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}
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block = block_of_triple(state, base);
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ret = build_triple(state, op, type, left, right,
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base->filename, base->line, base->col);
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|
|
@ -1491,7 +1506,7 @@ static void display_triple(FILE *fp, struct triple *ins)
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fprintf(fp, " %-10p", ins->param[i]);
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}
|
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for(; i < 2; i++) {
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printf(" ");
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fprintf(fp, " ");
|
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}
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fprintf(fp, " @ %s:%d.%d\n",
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ins->filename, ins->line, ins->col);
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|
|
@ -12248,6 +12263,7 @@ struct least_conflict {
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struct triple *ins;
|
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struct triple_reg_set *live;
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size_t count;
|
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int constraints;
|
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};
|
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static void least_conflict(struct compile_state *state,
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struct reg_block *blocks, struct triple_reg_set *live,
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|
|
@ -12257,19 +12273,13 @@ static void least_conflict(struct compile_state *state,
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struct live_range_edge *edge;
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struct triple_reg_set *set;
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size_t count;
|
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|
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#if 0
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#define HI() fprintf(stderr, "%-10p(%-15s) %d\n", ins, tops(ins->op), __LINE__)
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#else
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#define HI()
|
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#endif
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int constraints;
|
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|
||||
#warning "FIXME handle instructions with left hand sides..."
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/* Only instructions that introduce a new definition
|
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* can be the conflict instruction.
|
||||
*/
|
||||
if (!triple_is_def(state, ins)) {
|
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HI();
|
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return;
|
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}
|
||||
|
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|
|
@ -12280,22 +12290,25 @@ HI();
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|||
for(set = live; set; set = set->next) {
|
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struct live_range *lr;
|
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lr = conflict->rstate->lrd[set->member->id].lr;
|
||||
/* Ignore it if there cannot be an edge between these two nodes */
|
||||
if (!arch_regcm_intersect(conflict->ref_range->classes, lr->classes)) {
|
||||
continue;
|
||||
}
|
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for(edge = conflict->ref_range->edges; edge; edge = edge->next) {
|
||||
if (edge->node == lr) {
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||||
break;
|
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}
|
||||
}
|
||||
if (!edge && (lr != conflict->ref_range)) {
|
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HI();
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return;
|
||||
}
|
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count++;
|
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}
|
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if (count <= 1) {
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||||
HI();
|
||||
return;
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* See if there is an uncolored member in this subset.
|
||||
*/
|
||||
for(set = live; set; set = set->next) {
|
||||
|
|
@ -12306,11 +12319,79 @@ HI();
|
|||
}
|
||||
}
|
||||
if (!set && (conflict->ref_range != REG_UNSET)) {
|
||||
HI();
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* See if any of the live registers are constrained,
|
||||
* if not it won't be productive to pick this as
|
||||
* a conflict instruction.
|
||||
*/
|
||||
constraints = 0;
|
||||
for(set = live; set; set = set->next) {
|
||||
struct triple_set *uset;
|
||||
struct reg_info info;
|
||||
unsigned classes;
|
||||
unsigned cur_size, size;
|
||||
/* Skip this instruction */
|
||||
if (set->member == ins) {
|
||||
continue;
|
||||
}
|
||||
/* Find how many registers this value can potentially
|
||||
* be assigned to.
|
||||
*/
|
||||
classes = arch_type_to_regcm(state, set->member->type);
|
||||
size = regc_max_size(state, classes);
|
||||
|
||||
/* Find how many registers we allow this value to
|
||||
* be assigned to.
|
||||
*/
|
||||
info = arch_reg_lhs(state, set->member, 0);
|
||||
|
||||
/* If the value does not live in a register it
|
||||
* isn't constrained.
|
||||
*/
|
||||
if (info.reg == REG_UNNEEDED) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if ((info.reg == REG_UNSET) || (info.reg >= MAX_REGISTERS)) {
|
||||
cur_size = regc_max_size(state, info.regcm);
|
||||
} else {
|
||||
cur_size = 1;
|
||||
}
|
||||
|
||||
/* If there is no difference between potential and
|
||||
* actual register count there is not a constraint
|
||||
*/
|
||||
if (cur_size >= size) {
|
||||
continue;
|
||||
}
|
||||
|
||||
/* If this live_range feeds into conflict->inds
|
||||
* it isn't a constraint we can relieve.
|
||||
*/
|
||||
for(uset = set->member->use; uset; uset = uset->next) {
|
||||
if (uset->member == ins) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (uset) {
|
||||
continue;
|
||||
}
|
||||
constraints = 1;
|
||||
break;
|
||||
}
|
||||
/* Don't drop canidates with constraints */
|
||||
if (conflict->constraints && !constraints) {
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
#if 0
|
||||
fprintf(stderr, "conflict ins? %p %s count: %d constraints: %d\n",
|
||||
ins, tops(ins->op), count, constraints);
|
||||
#endif
|
||||
/* Find the instruction with the largest possible subset of
|
||||
* conflict ranges and that dominates any other instruction
|
||||
* with an equal sized set of conflicting ranges.
|
||||
|
|
@ -12322,6 +12403,7 @@ HI();
|
|||
/* Remember the canidate instruction */
|
||||
conflict->ins = ins;
|
||||
conflict->count = count;
|
||||
conflict->constraints = constraints;
|
||||
/* Free the old collection of live registers */
|
||||
for(set = conflict->live; set; set = next) {
|
||||
next = set->next;
|
||||
|
|
@ -12353,7 +12435,6 @@ HI();
|
|||
;
|
||||
}
|
||||
}
|
||||
HI();
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -12362,12 +12443,6 @@ static void find_range_conflict(struct compile_state *state,
|
|||
struct least_conflict *conflict)
|
||||
{
|
||||
|
||||
#if 0
|
||||
static void verify_blocks(struct compile_state *stae);
|
||||
verify_blocks(state);
|
||||
print_blocks(state, stderr);
|
||||
print_dominators(state, stderr);
|
||||
#endif
|
||||
/* there are 3 kinds ways conflicts can occure.
|
||||
* 1) the life time of 2 values simply overlap.
|
||||
* 2) the 2 values feed into the same instruction.
|
||||
|
|
@ -12390,34 +12465,22 @@ static void find_range_conflict(struct compile_state *state,
|
|||
conflict->rstate = rstate;
|
||||
conflict->ref_range = ref_range;
|
||||
conflict->ins = 0;
|
||||
conflict->count = 0;
|
||||
conflict->live = 0;
|
||||
conflict->count = 0;
|
||||
conflict->constraints = 0;
|
||||
walk_variable_lifetimes(state, rstate->blocks, least_conflict, conflict);
|
||||
|
||||
if (!conflict->ins) {
|
||||
struct live_range_edge *edge;
|
||||
struct live_range_def *lrd;
|
||||
fprintf(stderr, "edges:\n");
|
||||
for(edge = ref_range->edges; edge; edge = edge->next) {
|
||||
lrd = edge->node->defs;
|
||||
do {
|
||||
fprintf(stderr, " %-10p(%s)", lrd->def, tops(lrd->def->op));
|
||||
lrd = lrd->next;
|
||||
} while(lrd != edge->node->defs);
|
||||
fprintf(stderr, "|\n");
|
||||
}
|
||||
fprintf(stderr, "range:\n");
|
||||
lrd = ref_range->defs;
|
||||
do {
|
||||
fprintf(stderr, " %-10p(%s)", lrd->def, tops(lrd->def->op));
|
||||
lrd = lrd->next;
|
||||
} while(lrd != ref_range->defs);
|
||||
fprintf(stderr,"\n");
|
||||
internal_error(state, ref_range->defs->def, "No conflict ins?");
|
||||
}
|
||||
if (!conflict->live) {
|
||||
internal_error(state, ref_range->defs->def, "No conflict live?");
|
||||
}
|
||||
#if 0
|
||||
fprintf(stderr, "conflict ins: %p %s count: %d constraints: %d\n",
|
||||
conflict->ins, tops(conflict->ins->op),
|
||||
conflict->count, conflict->constraints);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -12452,6 +12515,13 @@ static struct triple *split_constrained_range(struct compile_state *state,
|
|||
* be assigned to.
|
||||
*/
|
||||
info = arch_reg_lhs(state, cset->member, 0);
|
||||
|
||||
/* If the register doesn't need a register
|
||||
* splitting it can't help.
|
||||
*/
|
||||
if (info.reg == REG_UNNEEDED) {
|
||||
continue;
|
||||
}
|
||||
#warning "FIXME do I need a call to arch_reg_rhs around here somewhere?"
|
||||
if ((info.reg == REG_UNSET) || (info.reg >= MAX_REGISTERS)) {
|
||||
cur_size = regc_max_size(state, info.regcm);
|
||||
|
|
@ -12497,6 +12567,10 @@ static int split_ranges(
|
|||
{
|
||||
struct triple *new;
|
||||
|
||||
#if 0
|
||||
fprintf(stderr, "split_ranges %d %s %p\n",
|
||||
rstate->passes, tops(range->defs->def->op), range->defs->def);
|
||||
#endif
|
||||
if ((range->color == REG_UNNEEDED) ||
|
||||
(rstate->passes >= rstate->max_passes)) {
|
||||
return 0;
|
||||
|
|
@ -12506,6 +12580,9 @@ static int split_ranges(
|
|||
if (arch_select_free_register(state, used, range->classes) == REG_UNSET) {
|
||||
struct least_conflict conflict;
|
||||
|
||||
#if 0
|
||||
fprintf(stderr, "find_range_conflict\n");
|
||||
#endif
|
||||
/* Find where in the set of registers the conflict
|
||||
* actually occurs.
|
||||
*/
|
||||
|
|
@ -12528,6 +12605,11 @@ static int split_ranges(
|
|||
*
|
||||
*/
|
||||
#warning "WISHLIST implement live range splitting..."
|
||||
#if 0
|
||||
print_blocks(state, stderr);
|
||||
print_dominators(state, stderr);
|
||||
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
|
@ -12536,7 +12618,13 @@ static int split_ranges(
|
|||
new->id = rstate->defs;
|
||||
rstate->defs++;
|
||||
#if 0
|
||||
fprintf(stderr, "new: %p\n", new);
|
||||
fprintf(stderr, "new: %p old: %s %p\n",
|
||||
new, tops(RHS(new, 0)->op), RHS(new, 0));
|
||||
#endif
|
||||
#if 0
|
||||
print_blocks(state, stderr);
|
||||
print_dominators(state, stderr);
|
||||
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -12717,17 +12805,29 @@ static int select_free_color(struct compile_state *state,
|
|||
arch_select_free_register(state, used, range->classes);
|
||||
}
|
||||
if (range->color == REG_UNSET) {
|
||||
struct live_range_def *lrd;
|
||||
int i;
|
||||
if (split_ranges(state, rstate, used, range)) {
|
||||
return 0;
|
||||
}
|
||||
for(edge = range->edges; edge; edge = edge->next) {
|
||||
if (edge->node->color == REG_UNSET) {
|
||||
continue;
|
||||
}
|
||||
warning(state, edge->node->defs->def, "reg %s",
|
||||
warning(state, edge->node->defs->def, "edge reg %s",
|
||||
arch_reg_str(edge->node->color));
|
||||
lrd = edge->node->defs;
|
||||
do {
|
||||
warning(state, lrd->def, " %s",
|
||||
tops(lrd->def->op));
|
||||
lrd = lrd->next;
|
||||
} while(lrd != edge->node->defs);
|
||||
}
|
||||
warning(state, range->defs->def, "range: ");
|
||||
lrd = range->defs;
|
||||
do {
|
||||
warning(state, lrd->def, " %s",
|
||||
tops(lrd->def->op));
|
||||
lrd = lrd->next;
|
||||
} while(lrd != range->defs);
|
||||
|
||||
warning(state, range->defs->def, "classes: %x",
|
||||
range->classes);
|
||||
for(i = 0; i < MAX_REGISTERS; i++) {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,41 @@
|
|||
static void main(void)
|
||||
{
|
||||
unsigned long loops0, loops1, loops2;
|
||||
unsigned long accum;
|
||||
|
||||
accum = 0;
|
||||
|
||||
loops0 = 10;
|
||||
do {
|
||||
unsigned short val;
|
||||
val = __builtin_inw(0x10e0);
|
||||
if (((val & 0x08) == 0) || (val == 1)) {
|
||||
break;
|
||||
}
|
||||
} while(--loops0);
|
||||
if (loops0 < 0) return;
|
||||
accum += loops0;
|
||||
|
||||
|
||||
loops1 = 20;
|
||||
do {
|
||||
unsigned short val;
|
||||
val = __builtin_inw(0x10e0);
|
||||
if (((val & 0x08) == 0) || (val == 1)) {
|
||||
break;
|
||||
}
|
||||
} while(--loops1);
|
||||
|
||||
loops2 = 30;
|
||||
do {
|
||||
unsigned short val;
|
||||
val = __builtin_inw(0x10e0);
|
||||
if (((val & 0x08) == 0) || (val == 1)) {
|
||||
break;
|
||||
}
|
||||
} while(--loops2);
|
||||
|
||||
accum += loops1 + loops0;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue