intel/fsp_baytrail: Rename from xx_DEV_FUNC
Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform. Change-Id: Id78e594ae6490d39df76317f8fc3381fe681dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
parent
beceea29d1
commit
d32efc9c7b
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@ -175,7 +175,7 @@ typedef struct soc_intel_fsp_baytrail_config config_t;
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void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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{
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acpi_header_t *header = &(fadt->header);
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struct device *lpcdev = pcidev_path_on_root(FADT_SOC_LPC_DEVFN);
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struct device *lpcdev = pcidev_path_on_root(PCH_DEVFN_LPC);
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u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0;
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config_t *config = config_of(lpcdev);
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@ -79,7 +79,7 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
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DEVTREE_CONST config_t *config;
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printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n");
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dev = pcidev_path_on_root(SOC_DEV_FUNC);
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dev = pcidev_path_on_root(SOC_DEVFN_SOC);
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config = config_of(dev);
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/* Set up default verb tables - Just HDMI audio */
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@ -142,26 +142,26 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
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continue;
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switch (dev->path.pci.devfn) {
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UPD_DEVICE_CHECK(SDIO_DEV_FUNC, PcdEnableSdio, "Sdio:\t\t\t");
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UPD_DEVICE_CHECK(SD_DEV_FUNC, PcdEnableSdcard, "Sdcard:\t\t\t");
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UPD_DEVICE_CHECK(SIO_DMA1_DEV_FUNC, PcdEnableDma0, "SIO Dma 0:\t\t");
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UPD_DEVICE_CHECK(I2C1_DEV_FUNC, PcdEnableI2C0, "SIO I2C0:\t\t");
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UPD_DEVICE_CHECK(I2C2_DEV_FUNC, PcdEnableI2C1, "SIO I2C1:\t\t");
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UPD_DEVICE_CHECK(I2C3_DEV_FUNC, PcdEnableI2C2, "SIO I2C2:\t\t");
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UPD_DEVICE_CHECK(I2C4_DEV_FUNC, PcdEnableI2C3, "SIO I2C3:\t\t");
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UPD_DEVICE_CHECK(I2C5_DEV_FUNC, PcdEnableI2C4, "SIO I2C4:\t\t");
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UPD_DEVICE_CHECK(I2C6_DEV_FUNC, PcdEnableI2C5, "SIO I2C5:\t\t");
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UPD_DEVICE_CHECK(I2C7_DEV_FUNC, PcdEnableI2C6, "SIO I2C6:\t\t");
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UPD_DEVICE_CHECK(SIO_DMA2_DEV_FUNC, PcdEnableDma1, "SIO Dma1:\t\t");
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UPD_DEVICE_CHECK(PWM1_DEV_FUNC, PcdEnablePwm0, "Pwm0:\t\t\t");
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UPD_DEVICE_CHECK(PWM2_DEV_FUNC, PcdEnablePwm1, "Pwm1:\t\t\t");
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UPD_DEVICE_CHECK(HSUART1_DEV_FUNC, PcdEnableHsuart0, "Hsuart0:\t\t");
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UPD_DEVICE_CHECK(HSUART2_DEV_FUNC, PcdEnableHsuart1, "Hsuart1:\t\t");
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UPD_DEVICE_CHECK(SPI_DEV_FUNC, PcdEnableSpi, "Spi:\t\t\t");
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UPD_DEVICE_CHECK(SATA_DEV_FUNC, PcdEnableSata, "SATA:\t\t\t");
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UPD_DEVICE_CHECK(HDA_DEV_FUNC, PcdEnableAzalia, "Azalia:\t\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_SDIO, PcdEnableSdio, "Sdio:\t\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_SD, PcdEnableSdcard, "Sdcard:\t\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_SIO_DMA1, PcdEnableDma0, "SIO Dma 0:\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_I2C1, PcdEnableI2C0, "SIO I2C0:\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_I2C2, PcdEnableI2C1, "SIO I2C1:\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_I2C3, PcdEnableI2C2, "SIO I2C2:\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_I2C4, PcdEnableI2C3, "SIO I2C3:\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_I2C5, PcdEnableI2C4, "SIO I2C4:\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_I2C6, PcdEnableI2C5, "SIO I2C5:\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_I2C7, PcdEnableI2C6, "SIO I2C6:\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_SIO_DMA2, PcdEnableDma1, "SIO Dma1:\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_PWM1, PcdEnablePwm0, "Pwm0:\t\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_PWM2, PcdEnablePwm1, "Pwm1:\t\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_HSUART1, PcdEnableHsuart0, "Hsuart0:\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_HSUART2, PcdEnableHsuart1, "Hsuart1:\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_SPI, PcdEnableSpi, "Spi:\t\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_SATA, PcdEnableSata, "SATA:\t\t\t");
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UPD_DEVICE_CHECK(SOC_DEVFN_HDA, PcdEnableAzalia, "Azalia:\t\t\t");
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case MIPI_DEV_FUNC: /* Camera / Image Signal Processing */
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case SOC_DEVFN_MIPI: /* Camera / Image Signal Processing */
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if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) {
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UpdData->ISPEnable = dev->enabled;
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} else {
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@ -174,24 +174,24 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
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printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n",
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dev->enabled?"Enabled":"Disabled");
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break;
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case EMMC_DEV_FUNC: /* EMMC 4.1*/
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case SOC_DEVFN_EMMC: /* EMMC 4.1*/
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if ((dev->enabled) &&
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(config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE))
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UpdData->PcdeMMCBootMode = EMMC_4_1 - EMMC_DISABLED;
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break;
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case MMC45_DEV_FUNC: /* MMC 4.5*/
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case SOC_DEVFN_MMC45: /* MMC 4.5*/
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if ((dev->enabled) &&
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(config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE))
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UpdData->PcdeMMCBootMode = EMMC_4_5 - EMMC_DISABLED;
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break;
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case XHCI_DEV_FUNC:
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case SOC_DEVFN_XHCI:
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UpdData->PcdEnableXhci = dev->enabled;
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break;
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case EHCI_DEV_FUNC:
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case SOC_DEVFN_EHCI:
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UpdData->PcdEnableXhci = !(dev->enabled);
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break;
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case LPE_DEV_FUNC:
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case SOC_DEVFN_LPE:
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if (dev->enabled)
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UpdData->PcdEnableLpe = config->LpeAcpiModeEnable;
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else
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@ -17,8 +17,6 @@
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#ifndef _BAYTRAIL_LPC_H_
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#define _BAYTRAIL_LPC_H_
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#define FADT_SOC_LPC_DEVFN PCI_DEVFN(0x1f, 0)
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/* PCI config registers in LPC bridge. */
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#define REVID 0x08
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#define ABASE 0x40 /* IO BAR */
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@ -26,40 +26,39 @@
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/* SoC transaction router */
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#define SOC_DEV 0x0
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#define SOC_FUNC 0
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# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC)
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# define SOC_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC)
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/* Graphics and Display */
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#define GFX_DEV 0x2
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#define GFX_FUNC 0
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# define GFX_DEV_FUNC PCI_DEVFN(GFX_DEV,GFX_FUNC)
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# define SOC_DEVFN_GFX PCI_DEVFN(GFX_DEV,GFX_FUNC)
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/* MIPI */
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#define MIPI_DEV 0x3
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#define MIPI_FUNC 0
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# define MIPI_DEV_FUNC PCI_DEVFN(MIPI_DEV,MIPI_FUNC)
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# define SOC_DEVFN_MIPI PCI_DEVFN(MIPI_DEV,MIPI_FUNC)
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/* SDIO Port */
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#define EMMC_DEV 0x10
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#define EMMC_FUNC 0
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# define EMMC_DEV_FUNC PCI_DEVFN(EMMC_DEV,EMMC_FUNC)
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# define SOC_DEVFN_EMMC PCI_DEVFN(EMMC_DEV,EMMC_FUNC)
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/* SDIO Port */
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#define SDIO_DEV 0x11
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#define SDIO_FUNC 0
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# define SDIO_DEV_FUNC PCI_DEVFN(SDIO_DEV,SDIO_FUNC)
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# define SOC_DEVFN_SDIO PCI_DEVFN(SDIO_DEV,SDIO_FUNC)
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/* SD Port */
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#define SD_DEV 0x12
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#define SD_FUNC 0
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# define SD_DEV_FUNC PCI_DEVFN(SD_DEV,SD_FUNC)
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# define SOC_DEVFN_SD PCI_DEVFN(SD_DEV,SD_FUNC)
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/* SATA */
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#define SATA_DEV 0x13
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#define SATA_FUNC 0
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# define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV,SATA_FUNC)
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# define SOC_DEVFN_SATA PCI_DEVFN(SATA_DEV,SATA_FUNC)
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/* xHCI */
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#define XHCI_DEV 0x14
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@ -67,22 +66,22 @@
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# define XHCI_FUS_REG 0xE0
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# define XHCI_FUNC_DISABLE (1 << 0)
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# define XHCI_USB2PR_REG 0xD0
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# define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
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# define SOC_DEVFN_XHCI PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
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/* LPE Audio */
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#define LPE_DEV 0x15
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#define LPE_FUNC 0
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# define LPE_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC)
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# define SOC_DEVFN_LPE PCI_DEVFN(LPE_DEV,LPE_FUNC)
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/* OTG */
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#define OTG_DEV 0x16
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#define OTG_FUNC 0
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# define OTG_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC)
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# define SOC_DEVFN_OTG PCI_DEVFN(LPE_DEV,LPE_FUNC)
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/* MMC Port */
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#define MMC45_DEV 0x17
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#define MMC45_FUNC 0
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# define MMC45_DEV_FUNC PCI_DEVFN(MMC45_DEV,MMC45_FUNC)
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# define SOC_DEVFN_MMC45 PCI_DEVFN(MMC45_DEV,MMC45_FUNC)
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/* Serial IO 1 */
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#define SIO1_DEV 0x18
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@ -102,24 +101,24 @@
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# define I2C6_FUNC 6
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# define I2C7_DEV SIO1_DEV
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# define I2C7_FUNC 7
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# define SIO_DMA1_DEV_FUNC PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC)
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# define I2C1_DEV_FUNC PCI_DEVFN(I2C1_DEV,I2C1_FUNC)
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# define I2C2_DEV_FUNC PCI_DEVFN(I2C2_DEV,I2C2_FUNC)
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# define I2C3_DEV_FUNC PCI_DEVFN(I2C3_DEV,I2C3_FUNC)
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# define I2C4_DEV_FUNC PCI_DEVFN(I2C4_DEV,I2C4_FUNC)
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# define I2C5_DEV_FUNC PCI_DEVFN(I2C5_DEV,I2C5_FUNC)
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# define I2C6_DEV_FUNC PCI_DEVFN(I2C6_DEV,I2C6_FUNC)
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# define I2C7_DEV_FUNC PCI_DEVFN(I2C7_DEV,I2C7_FUNC)
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# define SOC_DEVFN_SIO_DMA1 PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC)
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# define SOC_DEVFN_I2C1 PCI_DEVFN(I2C1_DEV,I2C1_FUNC)
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# define SOC_DEVFN_I2C2 PCI_DEVFN(I2C2_DEV,I2C2_FUNC)
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# define SOC_DEVFN_I2C3 PCI_DEVFN(I2C3_DEV,I2C3_FUNC)
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# define SOC_DEVFN_I2C4 PCI_DEVFN(I2C4_DEV,I2C4_FUNC)
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# define SOC_DEVFN_I2C5 PCI_DEVFN(I2C5_DEV,I2C5_FUNC)
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# define SOC_DEVFN_I2C6 PCI_DEVFN(I2C6_DEV,I2C6_FUNC)
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# define SOC_DEVFN_I2C7 PCI_DEVFN(I2C7_DEV,I2C7_FUNC)
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/* Trusted Execution Engine */
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#define TXE_DEV 0x1a
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#define TXE_FUNC 0
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# define TXE_DEV_FUNC PCI_DEVFN(TXE_DEV,TXE_FUNC)
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# define SOC_DEVFN_TXE PCI_DEVFN(TXE_DEV,TXE_FUNC)
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/* HD Audio */
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#define HDA_DEV 0x1b
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#define HDA_FUNC 0
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# define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV,HDA_FUNC)
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# define SOC_DEVFN_HDA PCI_DEVFN(HDA_DEV,HDA_FUNC)
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/* PCIe Ports */
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#define PCIE_DEV 0x1c
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@ -131,15 +130,15 @@
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# define PCIE_PORT3_FUNC 2
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# define PCIE_PORT4_DEV PCIE_DEV
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# define PCIE_PORT4_FUNC 3
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# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC)
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# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC)
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# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC)
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# define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC)
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# define SOC_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC)
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# define SOC_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC)
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# define SOC_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC)
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# define SOC_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC)
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/* EHCI */
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#define EHCI_DEV 0x1d
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#define EHCI_FUNC 0
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# define EHCI_DEV_FUNC PCI_DEVFN(EHCI_DEV,EHCI_FUNC)
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# define SOC_DEVFN_EHCI PCI_DEVFN(EHCI_DEV,EHCI_FUNC)
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/* Serial IO 2 */
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#define SIO2_DEV 0x1e
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@ -155,23 +154,24 @@
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# define HSUART2_FUNC 4
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# define SPI_DEV SIO2_DEV
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# define SPI_FUNC 5
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# define SIO_DMA2_DEV_FUNC PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC)
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# define PWM1_DEV_FUNC PCI_DEVFN(PWM1_DEV,PWM1_FUNC)
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# define PWM2_DEV_FUNC PCI_DEVFN(PWM2_DEV,PWM2_FUNC)
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# define HSUART1_DEV_FUNC PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC)
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# define HSUART2_DEV_FUNC PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC)
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# define SPI_DEV_FUNC PCI_DEVFN(SPI_DEV,SPI_FUNC)
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# define SOC_DEVFN_SIO_DMA2 PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC)
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# define SOC_DEVFN_PWM1 PCI_DEVFN(PWM1_DEV,PWM1_FUNC)
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# define SOC_DEVFN_PWM2 PCI_DEVFN(PWM2_DEV,PWM2_FUNC)
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# define SOC_DEVFN_HSUART1 PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC)
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# define SOC_DEVFN_HSUART2 PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC)
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# define SOC_DEVFN_SPI PCI_DEVFN(SPI_DEV,SPI_FUNC)
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/* Platform Controller Unit */
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#define PCU_DEV 0x1f
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# define LPC_DEV PCU_DEV
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# define LPC_FUNC 0
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# define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC)
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# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC)
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# define SMBUS_DEV PCU_DEV
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# define SMBUS_FUNC 3
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# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC)
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# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC)
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# define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
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# define SOC_DEVFN_SMBUS PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
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#define SOC_DEVID 0x0f00
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#define GFX_DEVID 0x0f31
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